Representative results only · all C code here is synthetic · no TI code is included or displayed details

Results are representative and informational only. Under Texas Instruments' C2000 software license terms, real TI SDK source code is confidential and licensed for internal use only, so no TI code is included, displayed, processed, or emitted here. All C code on this site is synthetic, written for this demo, with invented names and values that resemble typical power-converter firmware. The generated headers compile against this demo's sample firmware in CI; the "legacy" files used for the audit are illustrative and not guaranteed to compile on any target. Product ratings come from public IntelliPower data sheets; all circuit values and gains are invented. Independent demo, not affiliated with or endorsed by AMETEK, IntelliPower, or Texas Instruments. TI, C2000, and Code Composer Studio are trademarks of Texas Instruments.

How it works

Data sheet (CSV, cited)→Consistency gate→Board + chip + design→Rules → constants→Range, overflow, checks, staleness→C header or marked-block patch→Compile + known-answer test → review report

Any gate failure stops the line: nothing is written, and the report says which input caused it.

What a generated line looks like

/* Comparator DAC code for the positive hardware peak-current limit
 * = floor((target.v_ref / 2 + iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div)
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.r_shunt = 2 mohm  [board ups_ctrl_revA.yaml]
 *   board.g_amp = 10  [board ups_ctrl_revA.yaml]
 *   target.dac_div = 4096 counts  [target f28004x.yaml] */
#define UPS_IOUT_PKLIM_DAC_HI      3134u          /* 3134 counts, uint16 */

The formula, every input, and the file each came from travel with the constant. The review report typesets the same derivation, and a test checks that the typeset math equals the computed value.

Assumptions this demo makes

IntelliPower doesn't publish its firmware, board, or magnetics designs, so these are stated, not known. Values that rest on them are tagged assumption in the tools.

ProcessorTI C2000-class: F28004x (floating point, 100 MHz, 12-bit comparator DAC) by default; F2803x (no FPU, IQ20 fixed point, 60 MHz, 10-bit comparator DAC) as the legacy port. The pairing with these products is illustrative.
Power stageDouble-conversion online UPS: boost PFC rectifier, DC bus, inverter; the battery string connects to the bus through a bidirectional DC-DC stage (not modelled: a 36–92 V string can't sit on a 210–410 V bus).
Control boardInvented current sensing: 2 mΩ shunt, ×10 amplifier, mid-rail biased into a 3.3 V ADC. rev B swaps in a ×20 amplifier.
Design choicesInvented: 20 kHz switching, 1 µs dead time, 7% bus margin, 95% sensor headroom (h), hardware peak limit 3.5 × rated RMS current, 3:1 rated crest factor (CF), 95% maximum modulation index (m_max), 30 s overload delay.
BatteryLiFePO4 at 2.5 V per cell cutoff and 3.65 V full charge (generic chemistry figures).
Where constants liveIn C headers as #defines, the form the posting implies; other forms (tables, EEPROM images) would only change the output format.
MagneticsDesign limits are textbook assumptions (current density, window fill, flux margin); inductor requirements use a 30% ripple assumption and first-order formulas; drawings are synthetic.

Engineering principles

Single source of truth. Generated C code is never hand-edited; a test fails if it is.
Traceability. Every constant cites its formula and inputs, down to the data sheet quote.
Units are checked. A formula that adds volts to amps is an error.
Numeric honesty. Stated rounding, overflow is an error not a saturation, quantization error reported.
Fail closed. Any failure, nothing written.
Deterministic. Same inputs, byte-identical output, so diffs show only real changes.
Separation of concerns. Product, board, chip, and engineer design choices are independent inputs.
Evidence, not assertion. Hand-worked known answers are checked in compiled C code on every build.
Human authority. AI drafts; people approve.
Stated limits. See below.

Worked example: FA10507 current protection, data sheet to register

Two layers, as in real inverters. The data sheet's "Shutdown at 20% Overload" is a timed RMS overload handled in software (the delay is a design value; the sheet gives none). Separately, a hardware peak-current limit on the comparator protects against short circuits; it must sit well above rated peak current so 3:1 crest-factor loads such as computer power supplies don't trip it, and below the sensor's range. Inputs: 1500 VA and the overload level from the public data sheet; the peak-limit factor is an invented design value, the shunt and amplifier invented board values; reference and DAC width come from the chip profile. Check it on paper.

UPS_IOUT_RATED_A

I_{\text{rated}} = \frac{S}{V_{\text{out,nom}}}

= \frac{1500\,\text{VA}}{120\,\text{V}}

= 12.5\,\text{A}

UPS_IOUT_TRIP_A

I_{\text{trip}} = I_{\text{rated}} \cdot k_{\text{trip}}

= 12.5\,\text{A} \cdot 120\,\%

= 15\,\text{A}

UPS_IOUT_PK_LIMIT_A

I_{\text{pk,lim}} = k_{\text{pk}} \cdot I_{\text{rated}}

= 3.5 \cdot 12.5\,\text{A}

= 43.75\,\text{A}

UPS_IOUT_FS_PK_A

I_{\text{FS}} = \frac{\frac{V_{\text{ref}}}{2}}{R_{\text{sh}} \cdot G_{\text{amp}}}

= \frac{\frac{3.3\,\text{V}}{2}}{2\,\mathrm{m}\Omega \cdot 10}

= 82.5\,\text{A}

UPS_IOUT_PKLIM_DAC_HI

N_{\text{DAC,hi}} = \left\lfloor \frac{\frac{V_{\text{ref}}}{2} + I_{\text{pk,lim}} \cdot R_{\text{sh}} \cdot G_{\text{amp}}}{V_{\text{ref}}} \cdot D_{\text{DAC}} \right\rfloor

= \left\lfloor \frac{\frac{3.3\,\text{V}}{2} + 43.75\,\text{A} \cdot 2\,\mathrm{m}\Omega \cdot 10}{3.3\,\text{V}} \cdot 4096 \right\rfloor

= \left\lfloor 3134.06 \right\rfloor = 3134

check overload_below_pk_limit

\sqrt{2} \cdot I_{\text{trip}} < I_{\text{pk,lim}}

= \sqrt{2} \cdot 15\,\text{A} < 43.75\,\text{A}

\Rightarrow 21.2132\,\text{A} < 43.75\,\text{A}\quad \checkmark

check iout_sense_range

I_{\text{pk,lim}} \le h \cdot I_{\text{FS}}

= 43.75\,\text{A} \le 95\,\% \cdot 82.5\,\text{A}

\Rightarrow 43.75\,\text{A} \le 78.375\,\text{A}\quad \checkmark

Limitations

Sensing is simplified: dividers and the current shunt are drawn referenced to the controller. On an isolated unit a real design senses on the primary side or through isolation amplifiers or current transformers; the scale-factor math is the same.
One rule set assumes a boost-PFC, DC-bus, inverter topology. Real catalogs span topologies (isolated DC-DC stages, different battery paths) and would need rule sets per platform.
No TI hardware or TI compiler was used. The host C compiler (gcc in CI, clang locally) stands in for Code Composer Studio; it cannot catch C28x issues such as 16-bit char and int.
Product ratings are public; every circuit value, gain, firmware name, and the legacy code are invented.
Formulas are textbook relations, not IntelliPower's design rules. Loop gains are carried, never computed.
"Shutdown at 20% Overload" is read as a timed RMS trip at 120% of rated; its delay and the hardware peak-limit factor are invented. FA10434's swapped labels are resolved by a written override that a reviewer must confirm.
The AI eval runs on a synthetic corpus; it measures the pipeline, not real-world accuracy.
Per-unit calibration (test-station trims stored in EEPROM or flash) is a separate path not built here.

Extension: changing processors

TI publishes migration guides between C2000 generations. A processor change mostly moves clocks, pin and peripheral assignments, and number formats rather than the physics. Because the chip is a separate input here, a port is "swap the target profile, regenerate, diff": the F2803x-class profile in this demo regenerates the same product in IQ20 fixed point, and an IQ24 build, which tops out at ±128, refuses the 265 V input limit and 410 V bus setpoint as overflow errors (tested).