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Review: fa10434
FA10434 · IHT800-I-0.56Kw-120V-5060-120V-60-3LiHS-2U17 · board ups_ctrl rev A · target F28004x (float32)
inputs sha256 efd09c7981c3dfd0cb3aee2962f195ec2e0a29dbc22b8ee0da45166a54c1f410
Constants 29/31Checks passData sheet 3 for reviewStaleness currentC generated · modeled checks passed
Reviewer-visible overrides
- ds.iin_max: DS-10434 Rev.09172021 prints "7.4 Amps @90VAC Input, 560W Output" in the Input Frequency row and "50 or 60 Hz" in the Input Max Current row; the labels are swapped. Value taken from the Input Frequency row. Its 90 VAC test point is also below the sheet's own 102 V minimum input (120 V - 15%), so the input tolerance may be misprinted too (the sibling FA10449 reads -25%). Reviewer must confirm both with the data sheet owner.
- ds.batt_series_cells: DS-10434 lists three 12 V LiFePO4 modules in one string but not the cell count; 12 V LiFePO4 modules are normally 4 cells in series, so 3 x 4 = 12. Assumption for the demo; confirm with the battery supplier.
- ds.fin_nom_lo: DS-10434 Rev.09172021 prints the input frequency ("50 or 60 Hz") in the Input Max Current row; the labels are swapped. The unit accepts both mains frequencies, taken from that row. No tolerance is stated, so the input frequency window is not generated.
- ds.fin_nom_hi: Same swapped row as fin_nom_lo: "50 or 60 Hz", so the highest nominal input frequency is 60 Hz.
Constants
AC input
UPS_VIN_MIN_V102.0f
UPS_VIN_MAX_V138.0f
UPS_IIN_LIMIT_A7.4f
UPS_FIN_MIN_HZn/a (not on data sheet)
UPS_FIN_MAX_HZn/a (not on data sheet)
Rectifier / PFC
UPS_VBUS_MIN_V195.16147f
DC bus
UPS_VBUS_SET_V210.0f
UPS_VBUS_FS_V498.3f
UPS_VBUS_V_PER_COUNT0.12165527f
Inverter
UPS_VOUT_SET_V120.0f
UPS_VOUT_LO_V116.4f
UPS_VOUT_HI_V123.6f
UPS_VOUT_FS_PK_V501.65f
UPS_FOUT_HZ60.0f
UPS_FOUT_MODEUPS_FOUT_CHANGER
UPS_PWM_PERIOD_CNT2500u
UPS_PWM_DEADBAND_CNT100u
AC output
UPS_IOUT_RATED_A6.6666665f
UPS_IOUT_ALARM_A7.0f
UPS_IOUT_TRIP_A7.6666665f
UPS_OVERLOAD_DELAY_MS30000u
UPS_IOUT_PK_LIMIT_A23.333332f
UPS_IOUT_FS_PK_A82.5f
UPS_IOUT_PKLIM_DAC_HI2627u
UPS_IOUT_PKLIM_DAC_LO1469u
UPS_OVERLOAD_ACTIONUPS_OL_BYPASS
Battery
UPS_VBAT_NOM_V36.0f
UPS_VBAT_CUTOFF_V30.0f
UPS_VBAT_FS_V167.97f
Control loop (engineer-supplied)
UPS_VLOOP_KP0.8f
UPS_VLOOP_KI0.015f
Choose a constant to see how it's derived
UPS_VIN_MIN_V
Lowest input voltage the unit runs on before transferring to battery · pass
V_{\text{in,min}} = V_{\text{in,min}}^{\text{DS}} = 102\,\text{V}
Stored as float32 → 102.0f (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.vin_min | DS-10434 Rev.09172021 p1 (120 V - 15%) | 120 VAC, (-15% +15%) |
Generated C
/* Lowest input voltage the unit runs on before transferring to battery * = ds.vin_min * ds.vin_min = 102 V [DS-10434 Rev.09172021 p1 (120 V - 15%): "120 VAC, (-15% +15%)"] */ #define UPS_VIN_MIN_V 102.0f /* 102 V */
UPS_VIN_MAX_V
Highest input voltage the unit accepts · pass
V_{\text{in,max}} = V_{\text{in,max}}^{\text{DS}} = 138\,\text{V}
Stored as float32 → 138.0f (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.vin_max | DS-10434 Rev.09172021 p1 (120 V + 15%) | 120 VAC, (-15% +15%) |
Generated C
/* Highest input voltage the unit accepts * = ds.vin_max * ds.vin_max = 138 V [DS-10434 Rev.09172021 p1 (120 V + 15%): "120 VAC, (-15% +15%)"] */ #define UPS_VIN_MAX_V 138.0f /* 138 V */
UPS_IIN_LIMIT_A
Input current limit (data sheet maximum input current) · pass
I_{\text{in,max}} = I_{\text{in,max}}^{\text{DS}} = 7.4\,\text{A}
Stored as float32 → 7.4f, quantization error 1.29e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| ds.iin_max | OVERRIDE in fa10434.yaml (reason in header) |
Generated C
/* Input current limit (data sheet maximum input current) * = ds.iin_max * ds.iin_max = 7.4 A [OVERRIDE in fa10434.yaml (reason in header)] */ #define UPS_IIN_LIMIT_A 7.4f /* 7.4 A */
UPS_FIN_MIN_HZ
Lowest input frequency accepted (follower lock window / transfer to battery) · n/a
input ds.fin_tol_hz not in data sheet
f_{\text{in,min}} = f_{\text{in,lo}} - \Delta f_{\text{in}}
| Input | From | Data sheet text |
|---|---|---|
| ds.fin_nom_lo | OVERRIDE in fa10434.yaml (reason in header) |
Generated C
/* Lowest input frequency accepted (follower lock window / transfer to battery) * = ds.fin_nom_lo - ds.fin_tol_hz * ds.fin_nom_lo = 50 Hz [OVERRIDE in fa10434.yaml (reason in header)] * NOT GENERATED: input ds.fin_tol_hz not in data sheet */
UPS_FIN_MAX_HZ
Highest input frequency accepted (follower lock window / transfer to battery) · n/a
input ds.fin_tol_hz not in data sheet
f_{\text{in,max}} = f_{\text{in,hi}} + \Delta f_{\text{in}}
| Input | From | Data sheet text |
|---|---|---|
| ds.fin_nom_hi | OVERRIDE in fa10434.yaml (reason in header) |
Generated C
/* Highest input frequency accepted (follower lock window / transfer to battery) * = ds.fin_nom_hi + ds.fin_tol_hz * ds.fin_nom_hi = 60 Hz [OVERRIDE in fa10434.yaml (reason in header)] * NOT GENERATED: input ds.fin_tol_hz not in data sheet */
UPS_VBUS_MIN_V
A boost PFC stage must hold the bus above the peak of the highest input voltage · pass
V_{\text{bus,min}} = \sqrt{2} \cdot V_{\text{in,max}}
= \sqrt{2} \cdot 138\,\text{V}
= 195.161\,\text{V}
Stored as float32 → 195.16147f, quantization error 1.59e-06% (round half to even).
Generated C
/* A boost PFC stage must hold the bus above the peak of the highest input voltage * = sqrt(2) * vin_max */ #define UPS_VBUS_MIN_V 195.16147f /* 195.161 V */
UPS_VBUS_SET_V
DC bus regulation setpoint, bus minimum plus design margin, rounded up to 10 V · pass
V_{\text{bus,set}} = \left\lceil \frac{V_{\text{bus,min}} \cdot \left(1 + m_{\text{bus}}\right)}{10} \right\rceil \cdot 10
= \left\lceil \frac{195.161\,\text{V} \cdot \left(1 + 7\,\%\right)}{10} \right\rceil \cdot 10
= 210\,\text{V}
Stored as float32 → 210.0f (exact).
| Input | From | Data sheet text |
|---|---|---|
| design.vbus_margin | design fa10434.yaml | DC bus setpoint margin above rectified input peak |
Generated C
/* DC bus regulation setpoint, bus minimum plus design margin, rounded up to 10 V * = ceil(vbus_min * (1 + design.vbus_margin) / 10) * 10 * design.vbus_margin = 7 % [design fa10434.yaml] */ #define UPS_VBUS_SET_V 210.0f /* 210 V */
UPS_VBUS_FS_V
Bus voltage at ADC full scale (divider ratio times ADC reference) · pass
V_{\text{bus,FS}} = \frac{V_{\text{ref}} \cdot \left(R_{\text{bus,top}} + R_{\text{bus,bot}}\right)}{R_{\text{bus,bot}}}
= \frac{3.3\,\text{V} \cdot \left(1.5\,\mathrm{M}\Omega + 10\,\mathrm{k}\Omega\right)}{10\,\mathrm{k}\Omega}
= 498.3\,\text{V}
Stored as float32 → 498.3f, quantization error 2.45e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f28004x.yaml | internal 3.3 V ADC range selected |
| board.vbus_r_top | board ups_ctrl_revA.yaml | DC bus divider |
| board.vbus_r_bot | board ups_ctrl_revA.yaml | DC bus divider |
Generated C
/* Bus voltage at ADC full scale (divider ratio times ADC reference) * = target.v_ref * (board.vbus_r_top + board.vbus_r_bot) / board.vbus_r_bot * target.v_ref = 3.3 V [target f28004x.yaml] * board.vbus_r_top = 1.5 Mohm [board ups_ctrl_revA.yaml] * board.vbus_r_bot = 10 kohm [board ups_ctrl_revA.yaml] */ #define UPS_VBUS_FS_V 498.3f /* 498.3 V */
UPS_VBUS_V_PER_COUNT
Volts of bus per ADC count · pass
k_{\text{bus}} = \frac{V_{\text{bus,FS}}}{D_{\text{ADC}}}
= \frac{498.3\,\text{V}}{4096}
= 0.121655\,\text{V/count}
Stored as float32 → 0.12165527f (exact).
| Input | From | Data sheet text |
|---|---|---|
| target.adc_div | target f28004x.yaml | ADC transfer function: 1 LSB = V_ref / 4096 (TRM) |
Generated C
/* Volts of bus per ADC count * = vbus_fs / target.adc_div * target.adc_div = 4096 counts [target f28004x.yaml] */ #define UPS_VBUS_V_PER_COUNT 0.12165527f /* 0.121655 V/count */
UPS_VOUT_SET_V
Output voltage setpoint (RMS); a selectable output option would be its own variant and header (none built here) · pass
V_{\text{out}} = V_{\text{out,nom}} = 120\,\text{V}
Stored as float32 → 120.0f (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.vout_nom | DS-10434 Rev.09172021 p1 | 120 VAC, (±3%) |
Generated C
/* Output voltage setpoint (RMS); a selectable output option would be its own variant and header (none built here) * = ds.vout_nom * ds.vout_nom = 120 V [DS-10434 Rev.09172021 p1: "120 VAC, (+/-3%)"] */ #define UPS_VOUT_SET_V 120.0f /* 120 V */
UPS_VOUT_LO_V
Lower edge of the data sheet output regulation band · pass
V_{\text{out,lo}} = V_{\text{out}} \cdot \left(1 - k_{\text{reg}}\right)
= 120\,\text{V} \cdot \left(1 - 3\,\%\right)
= 116.4\,\text{V}
Stored as float32 → 116.4f, quantization error 1.31e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| ds.vout_tol_pct | DS-10434 Rev.09172021 p1 | 120 VAC, (±3%) |
Generated C
/* Lower edge of the data sheet output regulation band * = vout_set * (1 - ds.vout_tol_pct) * ds.vout_tol_pct = 3 % [DS-10434 Rev.09172021 p1: "120 VAC, (+/-3%)"] */ #define UPS_VOUT_LO_V 116.4f /* 116.4 V */
UPS_VOUT_HI_V
Upper edge of the data sheet output regulation band · pass
V_{\text{out,hi}} = V_{\text{out}} \cdot \left(1 + k_{\text{reg}}\right)
= 120\,\text{V} \cdot \left(1 + 3\,\%\right)
= 123.6\,\text{V}
Stored as float32 → 123.6f, quantization error 1.23e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| ds.vout_tol_pct | DS-10434 Rev.09172021 p1 | 120 VAC, (±3%) |
Generated C
/* Upper edge of the data sheet output regulation band * = vout_set * (1 + ds.vout_tol_pct) * ds.vout_tol_pct = 3 % [DS-10434 Rev.09172021 p1: "120 VAC, (+/-3%)"] */ #define UPS_VOUT_HI_V 123.6f /* 123.6 V */
UPS_VOUT_FS_PK_V
Peak output voltage at the edge of the mid-rail-biased sense range · pass
V_{\text{out,FS}} = \frac{\frac{V_{\text{ref}}}{2} \cdot \left(R_{\text{out,top}} + R_{\text{out,bot}}\right)}{R_{\text{out,bot}}}
= \frac{\frac{3.3\,\text{V}}{2} \cdot \left(1\,\mathrm{M}\Omega + 3.3\,\mathrm{k}\Omega\right)}{3.3\,\mathrm{k}\Omega}
= 501.65\,\text{V}
Stored as float32 → 501.65f, quantization error 1.22e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f28004x.yaml | internal 3.3 V ADC range selected |
| board.vout_r_top | board ups_ctrl_revA.yaml | AC output divider |
| board.vout_r_bot | board ups_ctrl_revA.yaml | AC output divider |
Generated C
/* Peak output voltage at the edge of the mid-rail-biased sense range * = target.v_ref / 2 * (board.vout_r_top + board.vout_r_bot) / board.vout_r_bot * target.v_ref = 3.3 V [target f28004x.yaml] * board.vout_r_top = 1 Mohm [board ups_ctrl_revA.yaml] * board.vout_r_bot = 3.3 kohm [board ups_ctrl_revA.yaml] */ #define UPS_VOUT_FS_PK_V 501.65f /* 501.65 V */
UPS_FOUT_HZ
Output frequency · pass
f_{\text{out}} = f_{\text{out}}^{\text{DS}} = 60\,\text{Hz}
Stored as float32 → 60.0f (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.fout_hz | DS-10434 Rev.09172021 p2 | 60 Hz +/- 1.5Hz, Changer |
Generated C
/* Output frequency * = ds.fout_hz * ds.fout_hz = 60 Hz [DS-10434 Rev.09172021 p2: "60 Hz +/- 1.5Hz, Changer"] */ #define UPS_FOUT_HZ 60.0f /* 60 Hz */
UPS_FOUT_MODE
Changer regenerates a fixed frequency; follower tracks the input · pass
\texttt{UPS\_FOUT\_MODE} = \texttt{UPS\_FOUT\_CHANGER} \quad (\text{data sheet: changer})
| Input | From | Data sheet text |
|---|---|---|
| ds.fout_mode | DS-10434 Rev.09172021 p2 | 60 Hz +/- 1.5Hz, Changer |
Generated C
/* Changer regenerates a fixed frequency; follower tracks the input * = ds.fout_mode * ds.fout_mode = changer [DS-10434 Rev.09172021 p2: "60 Hz +/- 1.5Hz, Changer"] */ #define UPS_FOUT_MODE UPS_FOUT_CHANGER
UPS_PWM_PERIOD_CNT
PWM period register, up-down (center-aligned) count mode as usual for inverters (TBPRD = f_clk / (2 f_sw)) · pass
N_{\text{PWM}} = \operatorname{round}\!\left(\frac{f_{\text{clk}}}{2 \cdot f_{\text{sw}}}\right)
= \operatorname{round}\!\left(\frac{100\,\text{MHz}}{2 \cdot 20\,\text{kHz}}\right)
= \operatorname{round}\!\left(2500\right) = 2500
Stored as uint16 → 2500u (exact).
| Input | From | Data sheet text |
|---|---|---|
| target.f_pwmclk | target f28004x.yaml | EPWMCLK = SYSCLK assumed |
| design.f_sw | design fa10434.yaml | inverter switching frequency (power engineering choice) |
Generated C
/* PWM period register, up-down (center-aligned) count mode as usual for inverters (TBPRD = f_clk / (2 f_sw)) * = round(target.f_pwmclk / (2 * design.f_sw)) * target.f_pwmclk = 100 MHz [target f28004x.yaml] * design.f_sw = 20 kHz [design fa10434.yaml] */ #define UPS_PWM_PERIOD_CNT 2500u /* 2500 counts, uint16 */
UPS_PWM_DEADBAND_CNT
Dead-time register · pass
N_{\text{DB}} = \left\lceil t_{\text{DB}} \cdot f_{\text{clk}} \right\rceil
= \left\lceil 1\,\mu\mathrm{s} \cdot 100\,\text{MHz} \right\rceil
= \left\lceil 100 \right\rceil = 100
Stored as uint16 → 100u (exact).
| Input | From | Data sheet text |
|---|---|---|
| design.t_deadband | design fa10434.yaml | gate-drive dead time for an IGBT bridge (power engineering choice) |
| target.f_pwmclk | target f28004x.yaml | EPWMCLK = SYSCLK assumed |
Generated C
/* Dead-time register * = ceil(design.t_deadband * target.f_pwmclk) * design.t_deadband = 1 us [design fa10434.yaml] * target.f_pwmclk = 100 MHz [target f28004x.yaml] */ #define UPS_PWM_DEADBAND_CNT 100u /* 100 counts, uint16 */
UPS_IOUT_RATED_A
Rated output current (RMS) · pass
I_{\text{rated}} = \frac{S}{V_{\text{out,nom}}}
= \frac{800\,\text{VA}}{120\,\text{V}}
= 6.66667\,\text{A}
Stored as float32 → 6.6666665f, quantization error 2.38e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| ds.power_va | DS-10434 Rev.09172021 p1 | 800 VA, 560 Watts |
| ds.vout_nom | DS-10434 Rev.09172021 p1 | 120 VAC, (±3%) |
Generated C
/* Rated output current (RMS) * = ds.power_va / ds.vout_nom * ds.power_va = 800 VA [DS-10434 Rev.09172021 p1: "800 VA, 560 Watts"] * ds.vout_nom = 120 V [DS-10434 Rev.09172021 p1: "120 VAC, (+/-3%)"] */ #define UPS_IOUT_RATED_A 6.6666665f /* 6.66667 A */
UPS_IOUT_ALARM_A
Overload alarm current (RMS) · pass
I_{\text{alarm}} = I_{\text{rated}} \cdot k_{\text{alarm}}
= 6.66667\,\text{A} \cdot 105\,\%
= 7\,\text{A}
Stored as float32 → 7.0f, quantization error 2.38e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| ds.overload_alarm_pct | DS-10434 Rev.09172021 p2 | Alarm at 105%, Bypass at 115% of Full Load |
Generated C
/* Overload alarm current (RMS) * = iout_rated * ds.overload_alarm_pct * ds.overload_alarm_pct = 105 % [DS-10434 Rev.09172021 p2: "Alarm at 105%, Bypass at 115% of Full Load"] */ #define UPS_IOUT_ALARM_A 7.0f /* 7 A */
UPS_IOUT_TRIP_A
Software overload trip level (RMS, timed; acts after UPS_OVERLOAD_DELAY_MS above this level) · pass
I_{\text{trip}} = I_{\text{rated}} \cdot k_{\text{trip}}
= 6.66667\,\text{A} \cdot 115\,\%
= 7.66667\,\text{A}
Stored as float32 → 7.6666665f, quantization error 3.11e-07% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| ds.overload_trip_pct | DS-10434 Rev.09172021 p2 | Alarm at 105%, Bypass at 115% of Full Load |
Generated C
/* Software overload trip level (RMS, timed; acts after UPS_OVERLOAD_DELAY_MS above this level) * = iout_rated * ds.overload_trip_pct * ds.overload_trip_pct = 115 % [DS-10434 Rev.09172021 p2: "Alarm at 105%, Bypass at 115% of Full Load"] */ #define UPS_IOUT_TRIP_A 7.6666665f /* 7.66667 A */
UPS_OVERLOAD_DELAY_MS
Time above the RMS trip level before the overload action (the data sheet gives no time) · pass
t_{\text{OL}} = t_{\text{OL}}^{\text{design}} = 30000\,\text{ms}
Stored as uint32 → 30000u (exact).
| Input | From | Data sheet text |
|---|---|---|
| design.overload_delay | design fa10434.yaml | time at the RMS trip level before the overload action; invented, the data sheet gives none |
Generated C
/* Time above the RMS trip level before the overload action (the data sheet gives no time) * = design.overload_delay * design.overload_delay = 30 s [design fa10434.yaml] */ #define UPS_OVERLOAD_DELAY_MS 30000u /* 30000 ms, uint32 */
UPS_IOUT_PK_LIMIT_A
Hardware peak-current limit (fast comparator, short-circuit protection); must clear the crest factor of rated nonlinear loads · pass
I_{\text{pk,lim}} = k_{\text{pk}} \cdot I_{\text{rated}}
= 3.5 \cdot 6.66667\,\text{A}
= 23.3333\,\text{A}
Stored as float32 → 23.333332f, quantization error 3.07e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| design.pk_limit_factor | design fa10434.yaml | hardware peak limit / rated RMS current: clears the rated crest factor with margin (checked) |
Generated C
/* Hardware peak-current limit (fast comparator, short-circuit protection); must clear the crest factor of rated nonlinear loads * = design.pk_limit_factor * iout_rated * design.pk_limit_factor = 3.5 [design fa10434.yaml] */ #define UPS_IOUT_PK_LIMIT_A 23.333332f /* 23.3333 A */
UPS_IOUT_FS_PK_A
Peak current at the edge of the mid-rail-biased current-sense range · pass
I_{\text{FS}} = \frac{\frac{V_{\text{ref}}}{2}}{R_{\text{sh}} \cdot G_{\text{amp}}}
= \frac{\frac{3.3\,\text{V}}{2}}{2\,\mathrm{m}\Omega \cdot 10}
= 82.5\,\text{A}
Stored as float32 → 82.5f (exact).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f28004x.yaml | internal 3.3 V ADC range selected |
| board.r_shunt | board ups_ctrl_revA.yaml | output current shunt; range must cover the hardware peak limit (~3.5x rated RMS) |
| board.g_amp | board ups_ctrl_revA.yaml | current-sense amplifier gain (rev A part) |
Generated C
/* Peak current at the edge of the mid-rail-biased current-sense range * = target.v_ref / 2 / (board.r_shunt * board.g_amp) * target.v_ref = 3.3 V [target f28004x.yaml] * board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml] * board.g_amp = 10 [board ups_ctrl_revA.yaml] */ #define UPS_IOUT_FS_PK_A 82.5f /* 82.5 A */
UPS_IOUT_PKLIM_DAC_HI
Comparator DAC code for the positive hardware peak-current limit · pass
N_{\text{DAC,hi}} = \left\lfloor \frac{\frac{V_{\text{ref}}}{2} + I_{\text{pk,lim}} \cdot R_{\text{sh}} \cdot G_{\text{amp}}}{V_{\text{ref}}} \cdot D_{\text{DAC}} \right\rfloor
= \left\lfloor \frac{\frac{3.3\,\text{V}}{2} + 23.3333\,\text{A} \cdot 2\,\mathrm{m}\Omega \cdot 10}{3.3\,\text{V}} \cdot 4096 \right\rfloor
= \left\lfloor 2627.23 \right\rfloor = 2627
Stored as uint16 → 2627u (exact).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f28004x.yaml | internal 3.3 V ADC range selected |
| board.r_shunt | board ups_ctrl_revA.yaml | output current shunt; range must cover the hardware peak limit (~3.5x rated RMS) |
| board.g_amp | board ups_ctrl_revA.yaml | current-sense amplifier gain (rev A part) |
| target.dac_div | target f28004x.yaml | CMPSS DAC: V = DACVAL x V_ref / 4096 (TRM) |
Generated C
/* Comparator DAC code for the positive hardware peak-current limit * = floor((target.v_ref / 2 + iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div) * target.v_ref = 3.3 V [target f28004x.yaml] * board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml] * board.g_amp = 10 [board ups_ctrl_revA.yaml] * target.dac_div = 4096 counts [target f28004x.yaml] */ #define UPS_IOUT_PKLIM_DAC_HI 2627u /* 2627 counts, uint16 */
UPS_IOUT_PKLIM_DAC_LO
Comparator DAC code for the negative hardware peak-current limit · pass
N_{\text{DAC,lo}} = \left\lceil \frac{\frac{V_{\text{ref}}}{2} - I_{\text{pk,lim}} \cdot R_{\text{sh}} \cdot G_{\text{amp}}}{V_{\text{ref}}} \cdot D_{\text{DAC}} \right\rceil
= \left\lceil \frac{\frac{3.3\,\text{V}}{2} - 23.3333\,\text{A} \cdot 2\,\mathrm{m}\Omega \cdot 10}{3.3\,\text{V}} \cdot 4096 \right\rceil
= \left\lceil 1468.77 \right\rceil = 1469
Stored as uint16 → 1469u (exact).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f28004x.yaml | internal 3.3 V ADC range selected |
| board.r_shunt | board ups_ctrl_revA.yaml | output current shunt; range must cover the hardware peak limit (~3.5x rated RMS) |
| board.g_amp | board ups_ctrl_revA.yaml | current-sense amplifier gain (rev A part) |
| target.dac_div | target f28004x.yaml | CMPSS DAC: V = DACVAL x V_ref / 4096 (TRM) |
Generated C
/* Comparator DAC code for the negative hardware peak-current limit * = ceil((target.v_ref / 2 - iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div) * target.v_ref = 3.3 V [target f28004x.yaml] * board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml] * board.g_amp = 10 [board ups_ctrl_revA.yaml] * target.dac_div = 4096 counts [target f28004x.yaml] */ #define UPS_IOUT_PKLIM_DAC_LO 1469u /* 1469 counts, uint16 */
UPS_OVERLOAD_ACTION
What the unit does when the RMS overload persists past the delay · pass
\texttt{UPS\_OVERLOAD\_ACTION} = \texttt{UPS\_OL\_BYPASS} \quad (\text{data sheet: bypass})
| Input | From | Data sheet text |
|---|---|---|
| ds.overload_action | DS-10434 Rev.09172021 p2 | Alarm at 105%, Bypass at 115% of Full Load |
Generated C
/* What the unit does when the RMS overload persists past the delay * = ds.overload_action * ds.overload_action = bypass [DS-10434 Rev.09172021 p2: "Alarm at 105%, Bypass at 115% of Full Load"] */ #define UPS_OVERLOAD_ACTION UPS_OL_BYPASS
UPS_VBAT_NOM_V
Battery string nominal voltage · pass
V_{\text{bat}} = V_{\text{bat}}^{\text{DS}} = 36\,\text{V}
Stored as float32 → 36.0f (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.batt_string_v | DS-10434 Rev.09172021 p2 | 36 VDC |
Generated C
/* Battery string nominal voltage * = ds.batt_string_v * ds.batt_string_v = 36 V [DS-10434 Rev.09172021 p2: "36 VDC"] */ #define UPS_VBAT_NOM_V 36.0f /* 36 V */
UPS_VBAT_CUTOFF_V
Low-battery shutdown voltage · pass
V_{\text{bat,cut}} = n_{\text{cells}} \cdot V_{\text{cell,cut}}
= 12\,\text{cells} \cdot 2.5\,\text{V}
= 30\,\text{V}
Stored as float32 → 30.0f (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.batt_series_cells | OVERRIDE in fa10434.yaml (reason in header) | |
| design.cell_cutoff_v | design fa10434.yaml | LiFePO4 per-cell discharge cutoff, generic chemistry figure |
Generated C
/* Low-battery shutdown voltage * = ds.batt_series_cells * design.cell_cutoff_v * ds.batt_series_cells = 12 cells [OVERRIDE in fa10434.yaml (reason in header)] * design.cell_cutoff_v = 2.5 V [design fa10434.yaml] */ #define UPS_VBAT_CUTOFF_V 30.0f /* 30 V */
UPS_VBAT_FS_V
Battery voltage at ADC full scale · pass
V_{\text{bat,FS}} = \frac{V_{\text{ref}} \cdot \left(R_{\text{bat,top}} + R_{\text{bat,bot}}\right)}{R_{\text{bat,bot}}}
= \frac{3.3\,\text{V} \cdot \left(499\,\mathrm{k}\Omega + 10\,\mathrm{k}\Omega\right)}{10\,\mathrm{k}\Omega}
= 167.97\,\text{V}
Stored as float32 → 167.97f, quantization error 7.27e-07% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f28004x.yaml | internal 3.3 V ADC range selected |
| board.vbat_r_top | board ups_ctrl_revA.yaml | battery divider |
| board.vbat_r_bot | board ups_ctrl_revA.yaml | battery divider |
Generated C
/* Battery voltage at ADC full scale * = target.v_ref * (board.vbat_r_top + board.vbat_r_bot) / board.vbat_r_bot * target.v_ref = 3.3 V [target f28004x.yaml] * board.vbat_r_top = 499 kohm [board ups_ctrl_revA.yaml] * board.vbat_r_bot = 10 kohm [board ups_ctrl_revA.yaml] */ #define UPS_VBAT_FS_V 167.97f /* 167.97 V */
UPS_VLOOP_KP
Voltage-loop proportional gain (tuned by power engineering) · pass
K_P = 0.8 \quad (\text{engineer-supplied})
Stored as float32 → 0.8f, quantization error 1.49e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| design.vloop_kp | design fa10434.yaml | voltage-loop proportional gain (engineer-tuned, invented) |
Generated C
/* Voltage-loop proportional gain (tuned by power engineering) * = design.vloop_kp * design.vloop_kp = 0.8 [design fa10434.yaml] * engineer-supplied value, carried through unchanged */ #define UPS_VLOOP_KP 0.8f /* 0.8 */
UPS_VLOOP_KI
Voltage-loop integral gain per control ISR (tuned by power engineering) · pass
K_I = 0.015 \quad (\text{engineer-supplied})
Stored as float32 → 0.015f, quantization error 2.24e-06% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| design.vloop_ki | design fa10434.yaml | voltage-loop integral gain per ISR (engineer-tuned, invented) |
Generated C
/* Voltage-loop integral gain per control ISR (tuned by power engineering) * = design.vloop_ki * design.vloop_ki = 0.015 [design fa10434.yaml] * engineer-supplied value, carried through unchanged */ #define UPS_VLOOP_KI 0.015f /* 0.015 */
Checks
| Check | Math | |
|---|---|---|
| pass | bus_above_output_peak The output peak at the top of the regulation band must fit under the bus at the inverter's maximum modulation index (room for modulation limits, dead time and device drop) | \sqrt{2} \cdot V_{\text{out,hi}} \le m_{\max} \cdot V_{\text{bus,set}} \cdot k_{\text{bridge}} = \sqrt{2} \cdot 123.6\,\text{V} \le 95\,\% \cdot 210\,\text{V} \cdot 1 \Rightarrow 174.797\,\text{V} \le 199.5\,\text{V}\quad \checkmark |
| pass | bus_sense_range Bus setpoint must sit inside the bus sensor's range with headroom | V_{\text{bus,set}} \le h \cdot V_{\text{bus,FS}} = 210\,\text{V} \le 95\,\% \cdot 498.3\,\text{V} \Rightarrow 210\,\text{V} \le 473.385\,\text{V}\quad \checkmark |
| pass | vout_sense_range Output peak at the top of the regulation band must sit inside the output sensor's range | \sqrt{2} \cdot V_{\text{out,hi}} \le h \cdot V_{\text{out,FS}} = \sqrt{2} \cdot 123.6\,\text{V} \le 95\,\% \cdot 501.65\,\text{V} \Rightarrow 174.797\,\text{V} \le 476.567\,\text{V}\quad \checkmark |
| pass | iout_sense_range Hardware peak limit must sit inside the current sensor's range, or the sensor saturates before the limit fires | I_{\text{pk,lim}} \le h \cdot I_{\text{FS}} = 23.3333\,\text{A} \le 95\,\% \cdot 82.5\,\text{A} \Rightarrow 23.3333\,\text{A} \le 78.375\,\text{A}\quad \checkmark |
| pass | overload_below_pk_limit A sinusoidal overload at the RMS trip level must stay under the hardware limit, so the timed overload acts first (crest-factor loads above rated are clipped by the hardware limit, as on real units) | \sqrt{2} \cdot I_{\text{trip}} < I_{\text{pk,lim}} = \sqrt{2} \cdot 7.66667\,\text{A} < 23.3333\,\text{A} \Rightarrow 10.8423\,\text{A} < 23.3333\,\text{A}\quad \checkmark |
| pass | crest_clears_pk_limit The peak of a rated nonlinear load (the assumed 3:1 crest factor at rated current) must clear the hardware limit, or normal loads trip the fast protection | CF \cdot I_{\text{rated}} < I_{\text{pk,lim}} = 3 \cdot 6.66667\,\text{A} < 23.3333\,\text{A} \Rightarrow 20\,\text{A} < 23.3333\,\text{A}\quad \checkmark |
| pass | crest_clears_dac_hi The DAC-derived positive trip threshold must clear the rated illustrative load peak after quantization | CF \cdot I_{\text{rated}} < \frac{\left(\frac{N_{\text{DAC,hi}}}{D_{\text{DAC}}} - 0.5\right) \cdot V_{\text{ref}}}{R_{\text{sh}} \cdot G_{\text{amp}}} = 3 \cdot 6.66667\,\text{A} < \frac{\left(\frac{2627}{4096} - 0.5\right) \cdot 3.3\,\text{V}}{2\,\mathrm{m}\Omega \cdot 10} \Rightarrow 20\,\text{A} < 23.324\,\text{A}\quad \checkmark |
| pass | crest_clears_dac_lo The magnitude of the DAC-derived negative trip threshold must clear the rated illustrative load peak after quantization | CF \cdot I_{\text{rated}} < \frac{\left(0.5 - \frac{N_{\text{DAC,lo}}}{D_{\text{DAC}}}\right) \cdot V_{\text{ref}}}{R_{\text{sh}} \cdot G_{\text{amp}}} = 3 \cdot 6.66667\,\text{A} < \frac{\left(0.5 - \frac{1469}{4096}\right) \cdot 3.3\,\text{V}}{2\,\mathrm{m}\Omega \cdot 10} \Rightarrow 20\,\text{A} < 23.324\,\text{A}\quad \checkmark |
| pass | dac_hi_in_range Positive peak-limit DAC code must exist on this chip's comparator DAC | N_{\text{DAC,hi}} \le N_{\text{DAC}} \Rightarrow 2627 \le 4095\quad \checkmark |
| pass | deadband_in_range Dead-time count must fit this chip's dead-band counter | N_{\text{DB}} \le N_{\text{DB,max}} \Rightarrow 100 \le 16383\quad \checkmark |
| pass | alarm_below_trip Overload alarm must come before the trip | I_{\text{alarm}} < I_{\text{trip}} \Rightarrow 7\,\text{A} < 7.66667\,\text{A}\quad \checkmark |
| pass | vbat_sense_range A fully charged battery must sit inside the battery sensor's range | n_{\text{cells}} \cdot V_{\text{cell,full}} \le h \cdot V_{\text{bat,FS}} = 12\,\text{cells} \cdot 3.65\,\text{V} \le 95\,\% \cdot 167.97\,\text{V} \Rightarrow 43.8\,\text{V} \le 159.572\,\text{V}\quad \checkmark |
| pass | cutoff_below_nominal Low-battery cutoff must be below nominal | V_{\text{bat,cut}} < V_{\text{bat}} \Rightarrow 30\,\text{V} < 36\,\text{V}\quad \checkmark |
| pass | input_voltage_order Minimum input voltage must not exceed maximum input voltage | V_{\text{in,min}}^{\text{DS}} \le V_{\text{in,max}}^{\text{DS}} \Rightarrow 102\,\text{V} \le 138\,\text{V}\quad \checkmark |
| pass | input_frequency_order Lower nominal input frequency must not exceed the upper frequency | f_{\text{in,lo}} \le f_{\text{in,hi}} \Rightarrow 50\,\text{Hz} \le 60\,\text{Hz}\quad \checkmark |
| pass | battery_cells_integer Battery series cell count must be a whole number | n_{\text{cells}} = \operatorname{round}\!\left(n_{\text{cells}}\right) = 12\,\text{cells} = \operatorname{round}\!\left(12\,\text{cells}\right) \Rightarrow 12 = 12\quad \checkmark |
| pass | battery_cells_positive Battery series cell count must be positive | n_{\text{cells}} > 0 = 12\,\text{cells} > 0 \Rightarrow 12 > 0\quad \checkmark |
| pass | output_regulation_nonnegative Output regulation tolerance must not be negative | k_{\text{reg}} \ge 0 = 3\,\% \ge 0 \Rightarrow 0.03 \ge 0\quad \checkmark |
| pass | output_regulation_below_100 Output regulation tolerance must be below 100% | k_{\text{reg}} < 1 = 3\,\% < 1 \Rightarrow 0.03 < 1\quad \checkmark |
Data sheet consistency
| Finding | Handling | |
|---|---|---|
| waived | row labeled 'Input Max Current (Amps):' should hold a current (A), but the cell reads like a frequency “Input Max Current (Amps): 50 or 60 Hz” | waived by override: DS-10434 Rev.09172021 prints "7.4 Amps @90VAC Input, 560W Output" in the Input Frequency row and "50 or 60 Hz" in the Input Max Current row; the labels are swapped. Value taken from the Input Frequency row. Its 90 VAC test point is also below the sheet's own 102 V minimum input (120 V - 15%), so the input tolerance may be misprinted too (the sibling FA10449 reads -25%). Reviewer must confirm both with the data sheet owner. |
| waived | row labeled 'Input Frequency (Hz, tolerance):' should hold a frequency (Hz), but the cell reads like a current “Input Frequency (Hz, tolerance): 7.4 Amps @90VAC Input, 560W Output” | waived by override: DS-10434 Rev.09172021 prints the input frequency ("50 or 60 Hz") in the Input Max Current row; the labels are swapped. The unit accepts both mains frequencies, taken from that row. No tolerance is stated, so the input frequency window is not generated. |
| waived | row labeled 'Input Frequency (Hz, tolerance):' should hold a frequency (Hz), but the cell reads like a current “Input Frequency (Hz, tolerance): 7.4 Amps @90VAC Input, 560W Output” | waived by override: Same swapped row as fin_nom_lo: "50 or 60 Hz", so the highest nominal input frequency is 60 Hz. |
Staleness of engineer-supplied values
| Value | Design basis | |
|---|---|---|
| pass | design.vloop_kp | designed for actual.f_sw = 20 kHz; now 20 kHz |
| pass | design.vloop_ki | designed for actual.f_sw = 20 kHz; now 20 kHz |
Generated C
calgen_fa10434.h (232 lines)
/* GENERATED by calgen 0.1.0 -- DO NOT EDIT. Regenerate from the spec files.
*
* variant : fa10434
* product : FA10434 IHT800-I-0.56Kw-120V-5060-120V-60-3LiHS-2U17
* ratings from DS-10434 Rev.09172021 (public IntelliPower data sheet)
* board : ups_ctrl rev A
* target : f28004x (default format float32)
* inverter: Full bridge - unipolar PWM (assumed hardware profile)
* PWM Hz : requested 20000; achieved 20000
* inputs : sha256 efd09c7981c3dfd0cb3aee2962f195ec2e0a29dbc22b8ee0da45166a54c1f410
*
* OVERRIDE ds.iin_max: DS-10434 Rev.09172021 prints "7.4 Amps @90VAC Input,
* 560W Output" in the Input Frequency row and "50 or 60 Hz" in the Input Max
* Current row; the labels are swapped. Value taken from the Input Frequency
* row. Its 90 VAC test point is also below the sheet's own 102 V minimum
* input (120 V - 15%), so the input tolerance may be misprinted too (the
* sibling FA10449 reads -25%). Reviewer must confirm both with the data
* sheet owner.
* OVERRIDE ds.batt_series_cells: DS-10434 lists three 12 V LiFePO4 modules in
* one string but not the cell count; 12 V LiFePO4 modules are normally 4
* cells in series, so 3 x 4 = 12. Assumption for the demo; confirm with the
* battery supplier.
* OVERRIDE ds.fin_nom_lo: DS-10434 Rev.09172021 prints the input frequency
* ("50 or 60 Hz") in the Input Max Current row; the labels are swapped. The
* unit accepts both mains frequencies, taken from that row. No tolerance is
* stated, so the input frequency window is not generated.
* OVERRIDE ds.fin_nom_hi: Same swapped row as fin_nom_lo: "50 or 60 Hz", so
* the highest nominal input frequency is 60 Hz.
*
* SYNTHETIC DEMO: firmware names and circuit values are invented; product ratings
* come from the public data sheet cited above. Not from any vendor SDK.
*/
#ifndef CALGEN_FA10434_H
#define CALGEN_FA10434_H
#include "calgen_types.h"
typedef float calgen_num_t; /* float target */
#define CALGEN_NUM(x) ((calgen_num_t)(x))
#define CALGEN_REAL(x) ((float)(x))
/* ==== AC input ============================================================== */
/* Lowest input voltage the unit runs on before transferring to battery
* = ds.vin_min
* ds.vin_min = 102 V [DS-10434 Rev.09172021 p1 (120 V - 15%): "120 VAC, (-15% +15%)"] */
#define UPS_VIN_MIN_V 102.0f /* 102 V */
/* Highest input voltage the unit accepts
* = ds.vin_max
* ds.vin_max = 138 V [DS-10434 Rev.09172021 p1 (120 V + 15%): "120 VAC, (-15% +15%)"] */
#define UPS_VIN_MAX_V 138.0f /* 138 V */
/* Input current limit (data sheet maximum input current)
* = ds.iin_max
* ds.iin_max = 7.4 A [OVERRIDE in fa10434.yaml (reason in header)] */
#define UPS_IIN_LIMIT_A 7.4f /* 7.4 A */
/* Lowest input frequency accepted (follower lock window / transfer to battery)
* = ds.fin_nom_lo - ds.fin_tol_hz
* ds.fin_nom_lo = 50 Hz [OVERRIDE in fa10434.yaml (reason in header)]
* NOT GENERATED: input ds.fin_tol_hz not in data sheet */
/* Highest input frequency accepted (follower lock window / transfer to battery)
* = ds.fin_nom_hi + ds.fin_tol_hz
* ds.fin_nom_hi = 60 Hz [OVERRIDE in fa10434.yaml (reason in header)]
* NOT GENERATED: input ds.fin_tol_hz not in data sheet */
/* ==== Rectifier / PFC ======================================================= */
/* A boost PFC stage must hold the bus above the peak of the highest input voltage
* = sqrt(2) * vin_max */
#define UPS_VBUS_MIN_V 195.16147f /* 195.161 V */
/* ==== DC bus ================================================================ */
/* DC bus regulation setpoint, bus minimum plus design margin, rounded up to 10 V
* = ceil(vbus_min * (1 + design.vbus_margin) / 10) * 10
* design.vbus_margin = 7 % [design fa10434.yaml] */
#define UPS_VBUS_SET_V 210.0f /* 210 V */
/* Bus voltage at ADC full scale (divider ratio times ADC reference)
* = target.v_ref * (board.vbus_r_top + board.vbus_r_bot) / board.vbus_r_bot
* target.v_ref = 3.3 V [target f28004x.yaml]
* board.vbus_r_top = 1.5 Mohm [board ups_ctrl_revA.yaml]
* board.vbus_r_bot = 10 kohm [board ups_ctrl_revA.yaml] */
#define UPS_VBUS_FS_V 498.3f /* 498.3 V */
/* Volts of bus per ADC count
* = vbus_fs / target.adc_div
* target.adc_div = 4096 counts [target f28004x.yaml] */
#define UPS_VBUS_V_PER_COUNT 0.12165527f /* 0.121655 V/count */
/* ==== Inverter ============================================================== */
/* Output voltage setpoint (RMS); a selectable output option would be its own variant and header (none built here)
* = ds.vout_nom
* ds.vout_nom = 120 V [DS-10434 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_VOUT_SET_V 120.0f /* 120 V */
/* Lower edge of the data sheet output regulation band
* = vout_set * (1 - ds.vout_tol_pct)
* ds.vout_tol_pct = 3 % [DS-10434 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_VOUT_LO_V 116.4f /* 116.4 V */
/* Upper edge of the data sheet output regulation band
* = vout_set * (1 + ds.vout_tol_pct)
* ds.vout_tol_pct = 3 % [DS-10434 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_VOUT_HI_V 123.6f /* 123.6 V */
/* Peak output voltage at the edge of the mid-rail-biased sense range
* = target.v_ref / 2 * (board.vout_r_top + board.vout_r_bot) / board.vout_r_bot
* target.v_ref = 3.3 V [target f28004x.yaml]
* board.vout_r_top = 1 Mohm [board ups_ctrl_revA.yaml]
* board.vout_r_bot = 3.3 kohm [board ups_ctrl_revA.yaml] */
#define UPS_VOUT_FS_PK_V 501.65f /* 501.65 V */
/* Output frequency
* = ds.fout_hz
* ds.fout_hz = 60 Hz [DS-10434 Rev.09172021 p2: "60 Hz +/- 1.5Hz, Changer"] */
#define UPS_FOUT_HZ 60.0f /* 60 Hz */
/* Changer regenerates a fixed frequency; follower tracks the input
* = ds.fout_mode
* ds.fout_mode = changer [DS-10434 Rev.09172021 p2: "60 Hz +/- 1.5Hz, Changer"] */
#define UPS_FOUT_MODE UPS_FOUT_CHANGER
/* PWM period register, up-down (center-aligned) count mode as usual for inverters (TBPRD = f_clk / (2 f_sw))
* = round(target.f_pwmclk / (2 * design.f_sw))
* target.f_pwmclk = 100 MHz [target f28004x.yaml]
* design.f_sw = 20 kHz [design fa10434.yaml] */
#define UPS_PWM_PERIOD_CNT 2500u /* 2500 counts, uint16 */
/* Dead-time register
* = ceil(design.t_deadband * target.f_pwmclk)
* design.t_deadband = 1 us [design fa10434.yaml]
* target.f_pwmclk = 100 MHz [target f28004x.yaml] */
#define UPS_PWM_DEADBAND_CNT 100u /* 100 counts, uint16 */
/* ==== AC output ============================================================= */
/* Rated output current (RMS)
* = ds.power_va / ds.vout_nom
* ds.power_va = 800 VA [DS-10434 Rev.09172021 p1: "800 VA, 560 Watts"]
* ds.vout_nom = 120 V [DS-10434 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_IOUT_RATED_A 6.6666665f /* 6.66667 A */
/* Overload alarm current (RMS)
* = iout_rated * ds.overload_alarm_pct
* ds.overload_alarm_pct = 105 % [DS-10434 Rev.09172021 p2: "Alarm at 105%, Bypass at 115% of Full Load"] */
#define UPS_IOUT_ALARM_A 7.0f /* 7 A */
/* Software overload trip level (RMS, timed; acts after UPS_OVERLOAD_DELAY_MS above this level)
* = iout_rated * ds.overload_trip_pct
* ds.overload_trip_pct = 115 % [DS-10434 Rev.09172021 p2: "Alarm at 105%, Bypass at 115% of Full Load"] */
#define UPS_IOUT_TRIP_A 7.6666665f /* 7.66667 A */
/* Time above the RMS trip level before the overload action (the data sheet gives no time)
* = design.overload_delay
* design.overload_delay = 30 s [design fa10434.yaml] */
#define UPS_OVERLOAD_DELAY_MS 30000u /* 30000 ms, uint32 */
/* Hardware peak-current limit (fast comparator, short-circuit protection); must clear the crest factor of rated nonlinear loads
* = design.pk_limit_factor * iout_rated
* design.pk_limit_factor = 3.5 [design fa10434.yaml] */
#define UPS_IOUT_PK_LIMIT_A 23.333332f /* 23.3333 A */
/* Peak current at the edge of the mid-rail-biased current-sense range
* = target.v_ref / 2 / (board.r_shunt * board.g_amp)
* target.v_ref = 3.3 V [target f28004x.yaml]
* board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml]
* board.g_amp = 10 [board ups_ctrl_revA.yaml] */
#define UPS_IOUT_FS_PK_A 82.5f /* 82.5 A */
/* Comparator DAC code for the positive hardware peak-current limit
* = floor((target.v_ref / 2 + iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div)
* target.v_ref = 3.3 V [target f28004x.yaml]
* board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml]
* board.g_amp = 10 [board ups_ctrl_revA.yaml]
* target.dac_div = 4096 counts [target f28004x.yaml] */
#define UPS_IOUT_PKLIM_DAC_HI 2627u /* 2627 counts, uint16 */
/* Comparator DAC code for the negative hardware peak-current limit
* = ceil((target.v_ref / 2 - iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div)
* target.v_ref = 3.3 V [target f28004x.yaml]
* board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml]
* board.g_amp = 10 [board ups_ctrl_revA.yaml]
* target.dac_div = 4096 counts [target f28004x.yaml] */
#define UPS_IOUT_PKLIM_DAC_LO 1469u /* 1469 counts, uint16 */
/* What the unit does when the RMS overload persists past the delay
* = ds.overload_action
* ds.overload_action = bypass [DS-10434 Rev.09172021 p2: "Alarm at 105%, Bypass at 115% of Full Load"] */
#define UPS_OVERLOAD_ACTION UPS_OL_BYPASS
/* ==== Battery =============================================================== */
/* Battery string nominal voltage
* = ds.batt_string_v
* ds.batt_string_v = 36 V [DS-10434 Rev.09172021 p2: "36 VDC"] */
#define UPS_VBAT_NOM_V 36.0f /* 36 V */
/* Low-battery shutdown voltage
* = ds.batt_series_cells * design.cell_cutoff_v
* ds.batt_series_cells = 12 cells [OVERRIDE in fa10434.yaml (reason in header)]
* design.cell_cutoff_v = 2.5 V [design fa10434.yaml] */
#define UPS_VBAT_CUTOFF_V 30.0f /* 30 V */
/* Battery voltage at ADC full scale
* = target.v_ref * (board.vbat_r_top + board.vbat_r_bot) / board.vbat_r_bot
* target.v_ref = 3.3 V [target f28004x.yaml]
* board.vbat_r_top = 499 kohm [board ups_ctrl_revA.yaml]
* board.vbat_r_bot = 10 kohm [board ups_ctrl_revA.yaml] */
#define UPS_VBAT_FS_V 167.97f /* 167.97 V */
/* ==== Control loop (engineer-supplied) ====================================== */
/* Voltage-loop proportional gain (tuned by power engineering)
* = design.vloop_kp
* design.vloop_kp = 0.8 [design fa10434.yaml]
* engineer-supplied value, carried through unchanged */
/* designed against: actual.f_sw = 20 kHz (staleness-tracked) */
#define UPS_VLOOP_KP 0.8f /* 0.8 */
/* Voltage-loop integral gain per control ISR (tuned by power engineering)
* = design.vloop_ki
* design.vloop_ki = 0.015 [design fa10434.yaml]
* engineer-supplied value, carried through unchanged */
/* designed against: actual.f_sw = 20 kHz (staleness-tracked) */
#define UPS_VLOOP_KI 0.015f /* 0.015 */
#endif /* CALGEN_FA10434_H */
Diff against committed version
No changes against the committed version.
Reviewed by
Date
Decision: approve / reject / waiver