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Results are representative and informational only. Under Texas Instruments' C2000 software license terms, real TI SDK source code is confidential and licensed for internal use only, so no TI code is included, displayed, processed, or emitted here. All C code on this site is synthetic, written for this demo, with invented names and values that resemble typical power-converter firmware. The generated headers compile against this demo's sample firmware in CI; the "legacy" files used for the audit are illustrative and not guaranteed to compile on any target. Product ratings come from public IntelliPower data sheets; all circuit values and gains are invented. Independent demo, not affiliated with or endorsed by AMETEK, IntelliPower, or Texas Instruments. TI, C2000, and Code Composer Studio are trademarks of Texas Instruments.

Review: fa10449

FA10449 · IHT650RM-I-0.5Kw-120-FC60-120-LiFeHS-3U17 · board ups_ctrl rev A · target F28004x (float32)
inputs sha256 60b71b7325300d8a9c755cafedd9db23dc480e54d06b4fb607c3242c977f9490
Constants 31/31Checks passData sheet 2 for reviewStaleness currentC generated · modeled checks passed

Constants

AC input
UPS_VIN_MIN_V90.0f
UPS_VIN_MAX_V138.0f
UPS_IIN_LIMIT_A7.9f
UPS_FIN_MIN_HZ55.0f
UPS_FIN_MAX_HZ65.0f
Rectifier / PFC
UPS_VBUS_MIN_V195.16147f
DC bus
UPS_VBUS_SET_V210.0f
UPS_VBUS_FS_V498.3f
UPS_VBUS_V_PER_COUNT0.12165527f
Inverter
UPS_VOUT_SET_V120.0f
UPS_VOUT_LO_V116.4f
UPS_VOUT_HI_V123.6f
UPS_VOUT_FS_PK_V501.65f
UPS_FOUT_HZ60.0f
UPS_FOUT_MODEUPS_FOUT_FOLLOWER
UPS_PWM_PERIOD_CNT2500u
UPS_PWM_DEADBAND_CNT100u
AC output
UPS_IOUT_RATED_A5.4166665f
UPS_IOUT_ALARM_A5.6875f
UPS_IOUT_TRIP_A6.2291665f
UPS_OVERLOAD_DELAY_MS30000u
UPS_IOUT_PK_LIMIT_A18.958332f
UPS_IOUT_FS_PK_A82.5f
UPS_IOUT_PKLIM_DAC_HI2518u
UPS_IOUT_PKLIM_DAC_LO1578u
UPS_OVERLOAD_ACTIONUPS_OL_SHUTDOWN
Battery
UPS_VBAT_NOM_V92.4f
UPS_VBAT_CUTOFF_V70.0f
UPS_VBAT_FS_V167.97f
Control loop (engineer-supplied)
UPS_VLOOP_KP0.8f
UPS_VLOOP_KI0.015f
Choose a constant to see how it's derived

UPS_VIN_MIN_V

Lowest input voltage the unit runs on before transferring to battery · pass

V_{\text{in,min}} = V_{\text{in,min}}^{\text{DS}} = 90\,\text{V}

Stored as float32 → 90.0f (exact).

InputFromData sheet text
ds.vin_minDS-10449 Rev.09172021 p1 (120 V - 25%)120 VAC, (-25% +15%)
Generated C
/* Lowest input voltage the unit runs on before transferring to battery
 * = ds.vin_min
 *   ds.vin_min = 90 V  [DS-10449 Rev.09172021 p1 (120 V - 25%): "120 VAC, (-25% +15%)"] */
#define UPS_VIN_MIN_V              90.0f          /* 90 V */

UPS_VIN_MAX_V

Highest input voltage the unit accepts · pass

V_{\text{in,max}} = V_{\text{in,max}}^{\text{DS}} = 138\,\text{V}

Stored as float32 → 138.0f (exact).

InputFromData sheet text
ds.vin_maxDS-10449 Rev.09172021 p1 (120 V + 15%)120 VAC, (-25% +15%)
Generated C
/* Highest input voltage the unit accepts
 * = ds.vin_max
 *   ds.vin_max = 138 V  [DS-10449 Rev.09172021 p1 (120 V + 15%): "120 VAC, (-25% +15%)"] */
#define UPS_VIN_MAX_V              138.0f         /* 138 V */

UPS_IIN_LIMIT_A

Input current limit (data sheet maximum input current) · pass

I_{\text{in,max}} = I_{\text{in,max}}^{\text{DS}} = 7.9\,\text{A}

Stored as float32 → 7.9f, quantization error 1.21e-06% (round half to even).

InputFromData sheet text
ds.iin_maxDS-10449 Rev.09172021 p17.9 Amps
Generated C
/* Input current limit (data sheet maximum input current)
 * = ds.iin_max
 *   ds.iin_max = 7.9 A  [DS-10449 Rev.09172021 p1: "7.9 Amps"] */
#define UPS_IIN_LIMIT_A            7.9f           /* 7.9 A */

UPS_FIN_MIN_HZ

Lowest input frequency accepted (follower lock window / transfer to battery) · pass

f_{\text{in,min}} = f_{\text{in,lo}} - \Delta f_{\text{in}}
= 60\,\text{Hz} - 5\,\text{Hz}
= 55\,\text{Hz}

Stored as float32 → 55.0f (exact).

InputFromData sheet text
ds.fin_nom_loDS-10449 Rev.09172021 p160 Hz, +/- 5.0 Hz
ds.fin_tol_hzDS-10449 Rev.09172021 p160 Hz, +/- 5.0 Hz
Generated C
/* Lowest input frequency accepted (follower lock window / transfer to battery)
 * = ds.fin_nom_lo - ds.fin_tol_hz
 *   ds.fin_nom_lo = 60 Hz  [DS-10449 Rev.09172021 p1: "60 Hz, +/- 5.0 Hz"]
 *   ds.fin_tol_hz = 5 Hz  [DS-10449 Rev.09172021 p1: "60 Hz, +/- 5.0 Hz"] */
#define UPS_FIN_MIN_HZ             55.0f          /* 55 Hz */

UPS_FIN_MAX_HZ

Highest input frequency accepted (follower lock window / transfer to battery) · pass

f_{\text{in,max}} = f_{\text{in,hi}} + \Delta f_{\text{in}}
= 60\,\text{Hz} + 5\,\text{Hz}
= 65\,\text{Hz}

Stored as float32 → 65.0f (exact).

InputFromData sheet text
ds.fin_nom_hiDS-10449 Rev.09172021 p160 Hz, +/- 5.0 Hz
ds.fin_tol_hzDS-10449 Rev.09172021 p160 Hz, +/- 5.0 Hz
Generated C
/* Highest input frequency accepted (follower lock window / transfer to battery)
 * = ds.fin_nom_hi + ds.fin_tol_hz
 *   ds.fin_nom_hi = 60 Hz  [DS-10449 Rev.09172021 p1: "60 Hz, +/- 5.0 Hz"]
 *   ds.fin_tol_hz = 5 Hz  [DS-10449 Rev.09172021 p1: "60 Hz, +/- 5.0 Hz"] */
#define UPS_FIN_MAX_HZ             65.0f          /* 65 Hz */

UPS_VBUS_MIN_V

A boost PFC stage must hold the bus above the peak of the highest input voltage · pass

V_{\text{bus,min}} = \sqrt{2} \cdot V_{\text{in,max}}
= \sqrt{2} \cdot 138\,\text{V}
= 195.161\,\text{V}

Stored as float32 → 195.16147f, quantization error 1.59e-06% (round half to even).

Generated C
/* A boost PFC stage must hold the bus above the peak of the highest input voltage
 * = sqrt(2) * vin_max */
#define UPS_VBUS_MIN_V             195.16147f     /* 195.161 V */

UPS_VBUS_SET_V

DC bus regulation setpoint, bus minimum plus design margin, rounded up to 10 V · pass

V_{\text{bus,set}} = \left\lceil \frac{V_{\text{bus,min}} \cdot \left(1 + m_{\text{bus}}\right)}{10} \right\rceil \cdot 10
= \left\lceil \frac{195.161\,\text{V} \cdot \left(1 + 7\,\%\right)}{10} \right\rceil \cdot 10
= 210\,\text{V}

Stored as float32 → 210.0f (exact).

InputFromData sheet text
design.vbus_margindesign fa10449.yamlDC bus setpoint margin above rectified input peak
Generated C
/* DC bus regulation setpoint, bus minimum plus design margin, rounded up to 10 V
 * = ceil(vbus_min * (1 + design.vbus_margin) / 10) * 10
 *   design.vbus_margin = 7 %  [design fa10449.yaml] */
#define UPS_VBUS_SET_V             210.0f         /* 210 V */

UPS_VBUS_FS_V

Bus voltage at ADC full scale (divider ratio times ADC reference) · pass

V_{\text{bus,FS}} = \frac{V_{\text{ref}} \cdot \left(R_{\text{bus,top}} + R_{\text{bus,bot}}\right)}{R_{\text{bus,bot}}}
= \frac{3.3\,\text{V} \cdot \left(1.5\,\mathrm{M}\Omega + 10\,\mathrm{k}\Omega\right)}{10\,\mathrm{k}\Omega}
= 498.3\,\text{V}

Stored as float32 → 498.3f, quantization error 2.45e-06% (round half to even).

InputFromData sheet text
target.v_reftarget f28004x.yamlinternal 3.3 V ADC range selected
board.vbus_r_topboard ups_ctrl_revA.yamlDC bus divider
board.vbus_r_botboard ups_ctrl_revA.yamlDC bus divider
Generated C
/* Bus voltage at ADC full scale (divider ratio times ADC reference)
 * = target.v_ref * (board.vbus_r_top + board.vbus_r_bot) / board.vbus_r_bot
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.vbus_r_top = 1.5 Mohm  [board ups_ctrl_revA.yaml]
 *   board.vbus_r_bot = 10 kohm  [board ups_ctrl_revA.yaml] */
#define UPS_VBUS_FS_V              498.3f         /* 498.3 V */

UPS_VBUS_V_PER_COUNT

Volts of bus per ADC count · pass

k_{\text{bus}} = \frac{V_{\text{bus,FS}}}{D_{\text{ADC}}}
= \frac{498.3\,\text{V}}{4096}
= 0.121655\,\text{V/count}

Stored as float32 → 0.12165527f (exact).

InputFromData sheet text
target.adc_divtarget f28004x.yamlADC transfer function: 1 LSB = V_ref / 4096 (TRM)
Generated C
/* Volts of bus per ADC count
 * = vbus_fs / target.adc_div
 *   target.adc_div = 4096 counts  [target f28004x.yaml] */
#define UPS_VBUS_V_PER_COUNT       0.12165527f    /* 0.121655 V/count */

UPS_VOUT_SET_V

Output voltage setpoint (RMS); a selectable output option would be its own variant and header (none built here) · pass

V_{\text{out}} = V_{\text{out,nom}} = 120\,\text{V}

Stored as float32 → 120.0f (exact).

InputFromData sheet text
ds.vout_nomDS-10449 Rev.09172021 p1120 VAC, (±3%)
Generated C
/* Output voltage setpoint (RMS); a selectable output option would be its own variant and header (none built here)
 * = ds.vout_nom
 *   ds.vout_nom = 120 V  [DS-10449 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_VOUT_SET_V             120.0f         /* 120 V */

UPS_VOUT_LO_V

Lower edge of the data sheet output regulation band · pass

V_{\text{out,lo}} = V_{\text{out}} \cdot \left(1 - k_{\text{reg}}\right)
= 120\,\text{V} \cdot \left(1 - 3\,\%\right)
= 116.4\,\text{V}

Stored as float32 → 116.4f, quantization error 1.31e-06% (round half to even).

InputFromData sheet text
ds.vout_tol_pctDS-10449 Rev.09172021 p1120 VAC, (±3%)
Generated C
/* Lower edge of the data sheet output regulation band
 * = vout_set * (1 - ds.vout_tol_pct)
 *   ds.vout_tol_pct = 3 %  [DS-10449 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_VOUT_LO_V              116.4f         /* 116.4 V */

UPS_VOUT_HI_V

Upper edge of the data sheet output regulation band · pass

V_{\text{out,hi}} = V_{\text{out}} \cdot \left(1 + k_{\text{reg}}\right)
= 120\,\text{V} \cdot \left(1 + 3\,\%\right)
= 123.6\,\text{V}

Stored as float32 → 123.6f, quantization error 1.23e-06% (round half to even).

InputFromData sheet text
ds.vout_tol_pctDS-10449 Rev.09172021 p1120 VAC, (±3%)
Generated C
/* Upper edge of the data sheet output regulation band
 * = vout_set * (1 + ds.vout_tol_pct)
 *   ds.vout_tol_pct = 3 %  [DS-10449 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_VOUT_HI_V              123.6f         /* 123.6 V */

UPS_VOUT_FS_PK_V

Peak output voltage at the edge of the mid-rail-biased sense range · pass

V_{\text{out,FS}} = \frac{\frac{V_{\text{ref}}}{2} \cdot \left(R_{\text{out,top}} + R_{\text{out,bot}}\right)}{R_{\text{out,bot}}}
= \frac{\frac{3.3\,\text{V}}{2} \cdot \left(1\,\mathrm{M}\Omega + 3.3\,\mathrm{k}\Omega\right)}{3.3\,\mathrm{k}\Omega}
= 501.65\,\text{V}

Stored as float32 → 501.65f, quantization error 1.22e-06% (round half to even).

InputFromData sheet text
target.v_reftarget f28004x.yamlinternal 3.3 V ADC range selected
board.vout_r_topboard ups_ctrl_revA.yamlAC output divider
board.vout_r_botboard ups_ctrl_revA.yamlAC output divider
Generated C
/* Peak output voltage at the edge of the mid-rail-biased sense range
 * = target.v_ref / 2 * (board.vout_r_top + board.vout_r_bot) / board.vout_r_bot
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.vout_r_top = 1 Mohm  [board ups_ctrl_revA.yaml]
 *   board.vout_r_bot = 3.3 kohm  [board ups_ctrl_revA.yaml] */
#define UPS_VOUT_FS_PK_V           501.65f        /* 501.65 V */

UPS_FOUT_HZ

Output frequency · pass

f_{\text{out}} = f_{\text{out}}^{\text{DS}} = 60\,\text{Hz}

Stored as float32 → 60.0f (exact).

InputFromData sheet text
ds.fout_hzDS-10449 Rev.09172021 p260 Hz, Follower
Generated C
/* Output frequency
 * = ds.fout_hz
 *   ds.fout_hz = 60 Hz  [DS-10449 Rev.09172021 p2: "60 Hz, Follower"] */
#define UPS_FOUT_HZ                60.0f          /* 60 Hz */

UPS_FOUT_MODE

Changer regenerates a fixed frequency; follower tracks the input · pass

\texttt{UPS\_FOUT\_MODE} = \texttt{UPS\_FOUT\_FOLLOWER} \quad (\text{data sheet: follower})
InputFromData sheet text
ds.fout_modeDS-10449 Rev.09172021 p260 Hz, Follower
Generated C
/* Changer regenerates a fixed frequency; follower tracks the input
 * = ds.fout_mode
 *   ds.fout_mode = follower  [DS-10449 Rev.09172021 p2: "60 Hz, Follower"] */
#define UPS_FOUT_MODE              UPS_FOUT_FOLLOWER

UPS_PWM_PERIOD_CNT

PWM period register, up-down (center-aligned) count mode as usual for inverters (TBPRD = f_clk / (2 f_sw)) · pass

N_{\text{PWM}} = \operatorname{round}\!\left(\frac{f_{\text{clk}}}{2 \cdot f_{\text{sw}}}\right)
= \operatorname{round}\!\left(\frac{100\,\text{MHz}}{2 \cdot 20\,\text{kHz}}\right)
= \operatorname{round}\!\left(2500\right) = 2500

Stored as uint16 → 2500u (exact).

InputFromData sheet text
target.f_pwmclktarget f28004x.yamlEPWMCLK = SYSCLK assumed
design.f_swdesign fa10449.yamlinverter switching frequency (power engineering choice)
Generated C
/* PWM period register, up-down (center-aligned) count mode as usual for inverters (TBPRD = f_clk / (2 f_sw))
 * = round(target.f_pwmclk / (2 * design.f_sw))
 *   target.f_pwmclk = 100 MHz  [target f28004x.yaml]
 *   design.f_sw = 20 kHz  [design fa10449.yaml] */
#define UPS_PWM_PERIOD_CNT         2500u          /* 2500 counts, uint16 */

UPS_PWM_DEADBAND_CNT

Dead-time register · pass

N_{\text{DB}} = \left\lceil t_{\text{DB}} \cdot f_{\text{clk}} \right\rceil
= \left\lceil 1\,\mu\mathrm{s} \cdot 100\,\text{MHz} \right\rceil
= \left\lceil 100 \right\rceil = 100

Stored as uint16 → 100u (exact).

InputFromData sheet text
design.t_deadbanddesign fa10449.yamlgate-drive dead time for an IGBT bridge (power engineering choice)
target.f_pwmclktarget f28004x.yamlEPWMCLK = SYSCLK assumed
Generated C
/* Dead-time register
 * = ceil(design.t_deadband * target.f_pwmclk)
 *   design.t_deadband = 1 us  [design fa10449.yaml]
 *   target.f_pwmclk = 100 MHz  [target f28004x.yaml] */
#define UPS_PWM_DEADBAND_CNT       100u           /* 100 counts, uint16 */

UPS_IOUT_RATED_A

Rated output current (RMS) · pass

I_{\text{rated}} = \frac{S}{V_{\text{out,nom}}}
= \frac{650\,\text{VA}}{120\,\text{V}}
= 5.41667\,\text{A}

Stored as float32 → 5.4166665f, quantization error 2.93e-06% (round half to even).

InputFromData sheet text
ds.power_vaDS-10449 Rev.09172021 p1650 VA, 500 Watts
ds.vout_nomDS-10449 Rev.09172021 p1120 VAC, (±3%)
Generated C
/* Rated output current (RMS)
 * = ds.power_va / ds.vout_nom
 *   ds.power_va = 650 VA  [DS-10449 Rev.09172021 p1: "650 VA, 500 Watts"]
 *   ds.vout_nom = 120 V  [DS-10449 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_IOUT_RATED_A           5.4166665f     /* 5.41667 A */

UPS_IOUT_ALARM_A

Overload alarm current (RMS) · pass

I_{\text{alarm}} = I_{\text{rated}} \cdot k_{\text{alarm}}
= 5.41667\,\text{A} \cdot 105\,\%
= 5.6875\,\text{A}

Stored as float32 → 5.6875f, quantization error 2.93e-06% (round half to even).

InputFromData sheet text
ds.overload_alarm_pctDS-10449 Rev.09172021 p2Alarm at 105%, Shutdown at 115% of Full Load
Generated C
/* Overload alarm current (RMS)
 * = iout_rated * ds.overload_alarm_pct
 *   ds.overload_alarm_pct = 105 %  [DS-10449 Rev.09172021 p2: "Alarm at 105%, Shutdown at 115% of Full Load"] */
#define UPS_IOUT_ALARM_A           5.6875f        /* 5.6875 A */

UPS_IOUT_TRIP_A

Software overload trip level (RMS, timed; acts after UPS_OVERLOAD_DELAY_MS above this level) · pass

I_{\text{trip}} = I_{\text{rated}} \cdot k_{\text{trip}}
= 5.41667\,\text{A} \cdot 115\,\%
= 6.22917\,\text{A}

Stored as float32 → 6.2291665f, quantization error 3.83e-07% (round half to even).

InputFromData sheet text
ds.overload_trip_pctDS-10449 Rev.09172021 p2Alarm at 105%, Shutdown at 115% of Full Load
Generated C
/* Software overload trip level (RMS, timed; acts after UPS_OVERLOAD_DELAY_MS above this level)
 * = iout_rated * ds.overload_trip_pct
 *   ds.overload_trip_pct = 115 %  [DS-10449 Rev.09172021 p2: "Alarm at 105%, Shutdown at 115% of Full Load"] */
#define UPS_IOUT_TRIP_A            6.2291665f     /* 6.22917 A */

UPS_OVERLOAD_DELAY_MS

Time above the RMS trip level before the overload action (the data sheet gives no time) · pass

t_{\text{OL}} = t_{\text{OL}}^{\text{design}} = 30000\,\text{ms}

Stored as uint32 → 30000u (exact).

InputFromData sheet text
design.overload_delaydesign fa10449.yamltime at the RMS trip level before the overload action; invented, the data sheet gives none
Generated C
/* Time above the RMS trip level before the overload action (the data sheet gives no time)
 * = design.overload_delay
 *   design.overload_delay = 30 s  [design fa10449.yaml] */
#define UPS_OVERLOAD_DELAY_MS      30000u         /* 30000 ms, uint32 */

UPS_IOUT_PK_LIMIT_A

Hardware peak-current limit (fast comparator, short-circuit protection); must clear the crest factor of rated nonlinear loads · pass

I_{\text{pk,lim}} = k_{\text{pk}} \cdot I_{\text{rated}}
= 3.5 \cdot 5.41667\,\text{A}
= 18.9583\,\text{A}

Stored as float32 → 18.958332f, quantization error 3.77e-06% (round half to even).

InputFromData sheet text
design.pk_limit_factordesign fa10449.yamlhardware peak limit / rated RMS current: clears the rated crest factor with margin (checked)
Generated C
/* Hardware peak-current limit (fast comparator, short-circuit protection); must clear the crest factor of rated nonlinear loads
 * = design.pk_limit_factor * iout_rated
 *   design.pk_limit_factor = 3.5  [design fa10449.yaml] */
#define UPS_IOUT_PK_LIMIT_A        18.958332f     /* 18.9583 A */

UPS_IOUT_FS_PK_A

Peak current at the edge of the mid-rail-biased current-sense range · pass

I_{\text{FS}} = \frac{\frac{V_{\text{ref}}}{2}}{R_{\text{sh}} \cdot G_{\text{amp}}}
= \frac{\frac{3.3\,\text{V}}{2}}{2\,\mathrm{m}\Omega \cdot 10}
= 82.5\,\text{A}

Stored as float32 → 82.5f (exact).

InputFromData sheet text
target.v_reftarget f28004x.yamlinternal 3.3 V ADC range selected
board.r_shuntboard ups_ctrl_revA.yamloutput current shunt; range must cover the hardware peak limit (~3.5x rated RMS)
board.g_ampboard ups_ctrl_revA.yamlcurrent-sense amplifier gain (rev A part)
Generated C
/* Peak current at the edge of the mid-rail-biased current-sense range
 * = target.v_ref / 2 / (board.r_shunt * board.g_amp)
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.r_shunt = 2 mohm  [board ups_ctrl_revA.yaml]
 *   board.g_amp = 10  [board ups_ctrl_revA.yaml] */
#define UPS_IOUT_FS_PK_A           82.5f          /* 82.5 A */

UPS_IOUT_PKLIM_DAC_HI

Comparator DAC code for the positive hardware peak-current limit · pass

N_{\text{DAC,hi}} = \left\lfloor \frac{\frac{V_{\text{ref}}}{2} + I_{\text{pk,lim}} \cdot R_{\text{sh}} \cdot G_{\text{amp}}}{V_{\text{ref}}} \cdot D_{\text{DAC}} \right\rfloor
= \left\lfloor \frac{\frac{3.3\,\text{V}}{2} + 18.9583\,\text{A} \cdot 2\,\mathrm{m}\Omega \cdot 10}{3.3\,\text{V}} \cdot 4096 \right\rfloor
= \left\lfloor 2518.63 \right\rfloor = 2518

Stored as uint16 → 2518u (exact).

InputFromData sheet text
target.v_reftarget f28004x.yamlinternal 3.3 V ADC range selected
board.r_shuntboard ups_ctrl_revA.yamloutput current shunt; range must cover the hardware peak limit (~3.5x rated RMS)
board.g_ampboard ups_ctrl_revA.yamlcurrent-sense amplifier gain (rev A part)
target.dac_divtarget f28004x.yamlCMPSS DAC: V = DACVAL x V_ref / 4096 (TRM)
Generated C
/* Comparator DAC code for the positive hardware peak-current limit
 * = floor((target.v_ref / 2 + iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div)
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.r_shunt = 2 mohm  [board ups_ctrl_revA.yaml]
 *   board.g_amp = 10  [board ups_ctrl_revA.yaml]
 *   target.dac_div = 4096 counts  [target f28004x.yaml] */
#define UPS_IOUT_PKLIM_DAC_HI      2518u          /* 2518 counts, uint16 */

UPS_IOUT_PKLIM_DAC_LO

Comparator DAC code for the negative hardware peak-current limit · pass

N_{\text{DAC,lo}} = \left\lceil \frac{\frac{V_{\text{ref}}}{2} - I_{\text{pk,lim}} \cdot R_{\text{sh}} \cdot G_{\text{amp}}}{V_{\text{ref}}} \cdot D_{\text{DAC}} \right\rceil
= \left\lceil \frac{\frac{3.3\,\text{V}}{2} - 18.9583\,\text{A} \cdot 2\,\mathrm{m}\Omega \cdot 10}{3.3\,\text{V}} \cdot 4096 \right\rceil
= \left\lceil 1577.37 \right\rceil = 1578

Stored as uint16 → 1578u (exact).

InputFromData sheet text
target.v_reftarget f28004x.yamlinternal 3.3 V ADC range selected
board.r_shuntboard ups_ctrl_revA.yamloutput current shunt; range must cover the hardware peak limit (~3.5x rated RMS)
board.g_ampboard ups_ctrl_revA.yamlcurrent-sense amplifier gain (rev A part)
target.dac_divtarget f28004x.yamlCMPSS DAC: V = DACVAL x V_ref / 4096 (TRM)
Generated C
/* Comparator DAC code for the negative hardware peak-current limit
 * = ceil((target.v_ref / 2 - iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div)
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.r_shunt = 2 mohm  [board ups_ctrl_revA.yaml]
 *   board.g_amp = 10  [board ups_ctrl_revA.yaml]
 *   target.dac_div = 4096 counts  [target f28004x.yaml] */
#define UPS_IOUT_PKLIM_DAC_LO      1578u          /* 1578 counts, uint16 */

UPS_OVERLOAD_ACTION

What the unit does when the RMS overload persists past the delay · pass

\texttt{UPS\_OVERLOAD\_ACTION} = \texttt{UPS\_OL\_SHUTDOWN} \quad (\text{data sheet: shutdown})
InputFromData sheet text
ds.overload_actionDS-10449 Rev.09172021 p2Alarm at 105%, Shutdown at 115% of Full Load
Generated C
/* What the unit does when the RMS overload persists past the delay
 * = ds.overload_action
 *   ds.overload_action = shutdown  [DS-10449 Rev.09172021 p2: "Alarm at 105%, Shutdown at 115% of Full Load"] */
#define UPS_OVERLOAD_ACTION        UPS_OL_SHUTDOWN

UPS_VBAT_NOM_V

Battery string nominal voltage · pass

V_{\text{bat}} = V_{\text{bat}}^{\text{DS}} = 92.4\,\text{V}

Stored as float32 → 92.4f, quantization error 1.65e-06% (round half to even).

InputFromData sheet text
ds.batt_string_vDS-10449 Rev.09172021 p292.4 VDC
Generated C
/* Battery string nominal voltage
 * = ds.batt_string_v
 *   ds.batt_string_v = 92.4 V  [DS-10449 Rev.09172021 p2: "92.4 VDC"] */
#define UPS_VBAT_NOM_V             92.4f          /* 92.4 V */

UPS_VBAT_CUTOFF_V

Low-battery shutdown voltage · pass

V_{\text{bat,cut}} = n_{\text{cells}} \cdot V_{\text{cell,cut}}
= 28\,\text{cells} \cdot 2.5\,\text{V}
= 70\,\text{V}

Stored as float32 → 70.0f (exact).

InputFromData sheet text
ds.batt_series_cellsDS-10449 Rev.09172021 p228 S1P Batteries
design.cell_cutoff_vdesign fa10449.yamlLiFePO4 per-cell discharge cutoff, generic chemistry figure
Generated C
/* Low-battery shutdown voltage
 * = ds.batt_series_cells * design.cell_cutoff_v
 *   ds.batt_series_cells = 28 cells  [DS-10449 Rev.09172021 p2: "28 S1P Batteries"]
 *   design.cell_cutoff_v = 2.5 V  [design fa10449.yaml] */
#define UPS_VBAT_CUTOFF_V          70.0f          /* 70 V */

UPS_VBAT_FS_V

Battery voltage at ADC full scale · pass

V_{\text{bat,FS}} = \frac{V_{\text{ref}} \cdot \left(R_{\text{bat,top}} + R_{\text{bat,bot}}\right)}{R_{\text{bat,bot}}}
= \frac{3.3\,\text{V} \cdot \left(499\,\mathrm{k}\Omega + 10\,\mathrm{k}\Omega\right)}{10\,\mathrm{k}\Omega}
= 167.97\,\text{V}

Stored as float32 → 167.97f, quantization error 7.27e-07% (round half to even).

InputFromData sheet text
target.v_reftarget f28004x.yamlinternal 3.3 V ADC range selected
board.vbat_r_topboard ups_ctrl_revA.yamlbattery divider
board.vbat_r_botboard ups_ctrl_revA.yamlbattery divider
Generated C
/* Battery voltage at ADC full scale
 * = target.v_ref * (board.vbat_r_top + board.vbat_r_bot) / board.vbat_r_bot
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.vbat_r_top = 499 kohm  [board ups_ctrl_revA.yaml]
 *   board.vbat_r_bot = 10 kohm  [board ups_ctrl_revA.yaml] */
#define UPS_VBAT_FS_V              167.97f        /* 167.97 V */

UPS_VLOOP_KP

Voltage-loop proportional gain (tuned by power engineering) · pass

K_P = 0.8 \quad (\text{engineer-supplied})

Stored as float32 → 0.8f, quantization error 1.49e-06% (round half to even).

InputFromData sheet text
design.vloop_kpdesign fa10449.yamlvoltage-loop proportional gain (engineer-tuned, invented)
Generated C
/* Voltage-loop proportional gain (tuned by power engineering)
 * = design.vloop_kp
 *   design.vloop_kp = 0.8  [design fa10449.yaml]
 *   engineer-supplied value, carried through unchanged */
#define UPS_VLOOP_KP               0.8f           /* 0.8 */

UPS_VLOOP_KI

Voltage-loop integral gain per control ISR (tuned by power engineering) · pass

K_I = 0.015 \quad (\text{engineer-supplied})

Stored as float32 → 0.015f, quantization error 2.24e-06% (round half to even).

InputFromData sheet text
design.vloop_kidesign fa10449.yamlvoltage-loop integral gain per ISR (engineer-tuned, invented)
Generated C
/* Voltage-loop integral gain per control ISR (tuned by power engineering)
 * = design.vloop_ki
 *   design.vloop_ki = 0.015  [design fa10449.yaml]
 *   engineer-supplied value, carried through unchanged */
#define UPS_VLOOP_KI               0.015f         /* 0.015 */

Checks

CheckMath
passbus_above_output_peak
The output peak at the top of the regulation band must fit under the bus at the inverter's maximum modulation index (room for modulation limits, dead time and device drop)
\sqrt{2} \cdot V_{\text{out,hi}} \le m_{\max} \cdot V_{\text{bus,set}} \cdot k_{\text{bridge}}
= \sqrt{2} \cdot 123.6\,\text{V} \le 95\,\% \cdot 210\,\text{V} \cdot 1
\Rightarrow 174.797\,\text{V} \le 199.5\,\text{V}\quad \checkmark
passbus_sense_range
Bus setpoint must sit inside the bus sensor's range with headroom
V_{\text{bus,set}} \le h \cdot V_{\text{bus,FS}}
= 210\,\text{V} \le 95\,\% \cdot 498.3\,\text{V}
\Rightarrow 210\,\text{V} \le 473.385\,\text{V}\quad \checkmark
passvout_sense_range
Output peak at the top of the regulation band must sit inside the output sensor's range
\sqrt{2} \cdot V_{\text{out,hi}} \le h \cdot V_{\text{out,FS}}
= \sqrt{2} \cdot 123.6\,\text{V} \le 95\,\% \cdot 501.65\,\text{V}
\Rightarrow 174.797\,\text{V} \le 476.567\,\text{V}\quad \checkmark
passiout_sense_range
Hardware peak limit must sit inside the current sensor's range, or the sensor saturates before the limit fires
I_{\text{pk,lim}} \le h \cdot I_{\text{FS}}
= 18.9583\,\text{A} \le 95\,\% \cdot 82.5\,\text{A}
\Rightarrow 18.9583\,\text{A} \le 78.375\,\text{A}\quad \checkmark
passoverload_below_pk_limit
A sinusoidal overload at the RMS trip level must stay under the hardware limit, so the timed overload acts first (crest-factor loads above rated are clipped by the hardware limit, as on real units)
\sqrt{2} \cdot I_{\text{trip}} < I_{\text{pk,lim}}
= \sqrt{2} \cdot 6.22917\,\text{A} < 18.9583\,\text{A}
\Rightarrow 8.80937\,\text{A} < 18.9583\,\text{A}\quad \checkmark
passcrest_clears_pk_limit
The peak of a rated nonlinear load (the assumed 3:1 crest factor at rated current) must clear the hardware limit, or normal loads trip the fast protection
CF \cdot I_{\text{rated}} < I_{\text{pk,lim}}
= 3 \cdot 5.41667\,\text{A} < 18.9583\,\text{A}
\Rightarrow 16.25\,\text{A} < 18.9583\,\text{A}\quad \checkmark
passcrest_clears_dac_hi
The DAC-derived positive trip threshold must clear the rated illustrative load peak after quantization
CF \cdot I_{\text{rated}} < \frac{\left(\frac{N_{\text{DAC,hi}}}{D_{\text{DAC}}} - 0.5\right) \cdot V_{\text{ref}}}{R_{\text{sh}} \cdot G_{\text{amp}}}
= 3 \cdot 5.41667\,\text{A} < \frac{\left(\frac{2518}{4096} - 0.5\right) \cdot 3.3\,\text{V}}{2\,\mathrm{m}\Omega \cdot 10}
\Rightarrow 16.25\,\text{A} < 18.9331\,\text{A}\quad \checkmark
passcrest_clears_dac_lo
The magnitude of the DAC-derived negative trip threshold must clear the rated illustrative load peak after quantization
CF \cdot I_{\text{rated}} < \frac{\left(0.5 - \frac{N_{\text{DAC,lo}}}{D_{\text{DAC}}}\right) \cdot V_{\text{ref}}}{R_{\text{sh}} \cdot G_{\text{amp}}}
= 3 \cdot 5.41667\,\text{A} < \frac{\left(0.5 - \frac{1578}{4096}\right) \cdot 3.3\,\text{V}}{2\,\mathrm{m}\Omega \cdot 10}
\Rightarrow 16.25\,\text{A} < 18.9331\,\text{A}\quad \checkmark
passdac_hi_in_range
Positive peak-limit DAC code must exist on this chip's comparator DAC
N_{\text{DAC,hi}} \le N_{\text{DAC}}
\Rightarrow 2518 \le 4095\quad \checkmark
passdeadband_in_range
Dead-time count must fit this chip's dead-band counter
N_{\text{DB}} \le N_{\text{DB,max}}
\Rightarrow 100 \le 16383\quad \checkmark
passalarm_below_trip
Overload alarm must come before the trip
I_{\text{alarm}} < I_{\text{trip}}
\Rightarrow 5.6875\,\text{A} < 6.22917\,\text{A}\quad \checkmark
passvbat_sense_range
A fully charged battery must sit inside the battery sensor's range
n_{\text{cells}} \cdot V_{\text{cell,full}} \le h \cdot V_{\text{bat,FS}}
= 28\,\text{cells} \cdot 3.65\,\text{V} \le 95\,\% \cdot 167.97\,\text{V}
\Rightarrow 102.2\,\text{V} \le 159.572\,\text{V}\quad \checkmark
passcutoff_below_nominal
Low-battery cutoff must be below nominal
V_{\text{bat,cut}} < V_{\text{bat}}
\Rightarrow 70\,\text{V} < 92.4\,\text{V}\quad \checkmark
passinput_voltage_order
Minimum input voltage must not exceed maximum input voltage
V_{\text{in,min}}^{\text{DS}} \le V_{\text{in,max}}^{\text{DS}}
\Rightarrow 90\,\text{V} \le 138\,\text{V}\quad \checkmark
passinput_frequency_order
Lower nominal input frequency must not exceed the upper frequency
f_{\text{in,lo}} \le f_{\text{in,hi}}
\Rightarrow 60\,\text{Hz} \le 60\,\text{Hz}\quad \checkmark
passbattery_cells_integer
Battery series cell count must be a whole number
n_{\text{cells}} = \operatorname{round}\!\left(n_{\text{cells}}\right)
= 28\,\text{cells} = \operatorname{round}\!\left(28\,\text{cells}\right)
\Rightarrow 28 = 28\quad \checkmark
passbattery_cells_positive
Battery series cell count must be positive
n_{\text{cells}} > 0
= 28\,\text{cells} > 0
\Rightarrow 28 > 0\quad \checkmark
passoutput_regulation_nonnegative
Output regulation tolerance must not be negative
k_{\text{reg}} \ge 0
= 3\,\% \ge 0
\Rightarrow 0.03 \ge 0\quad \checkmark
passoutput_regulation_below_100
Output regulation tolerance must be below 100%
k_{\text{reg}} < 1
= 3\,\% < 1
\Rightarrow 0.03 < 1\quad \checkmark

Data sheet consistency

FindingHandling
flaggedmodel string has an FC token (read as Frequency Changer; naming convention inferred, not documented) but the output row says Follower
“IHT650RM-I-0.5Kw-120-FC60-120-LiFeHS-3U17”
“60 Hz, Follower”		needs engineer review
flaggedunit description says Frequency Changer but the output frequency row says Follower
“650VA, 500W, 120VAC 60Hz Input and 120VAC 60Hz Output, Frequency Changer, Non-Isolated, Power Factor Corrected,1/2 Rack ”
“60 Hz, Follower”		needs engineer review

Staleness of engineer-supplied values

ValueDesign basis
passdesign.vloop_kpdesigned for actual.f_sw = 20 kHz; now 20 kHz
passdesign.vloop_kidesigned for actual.f_sw = 20 kHz; now 20 kHz

Generated C

calgen_fa10449.h (216 lines)
/* GENERATED by calgen 0.1.0 -- DO NOT EDIT. Regenerate from the spec files.
 *
 * variant : fa10449
 * product : FA10449  IHT650RM-I-0.5Kw-120-FC60-120-LiFeHS-3U17
 *           ratings from DS-10449 Rev.09172021 (public IntelliPower data sheet)
 * board   : ups_ctrl rev A
 * target  : f28004x (default format float32)
 * inverter: Full bridge - unipolar PWM (assumed hardware profile)
 * PWM Hz  : requested 20000; achieved 20000
 * inputs  : sha256 60b71b7325300d8a9c755cafedd9db23dc480e54d06b4fb607c3242c977f9490
 *
 * SYNTHETIC DEMO: firmware names and circuit values are invented; product ratings
 * come from the public data sheet cited above. Not from any vendor SDK.
 */
#ifndef CALGEN_FA10449_H
#define CALGEN_FA10449_H

#include "calgen_types.h"

typedef float calgen_num_t;  /* float target */
#define CALGEN_NUM(x)  ((calgen_num_t)(x))
#define CALGEN_REAL(x) ((float)(x))

/* ==== AC input ============================================================== */

/* Lowest input voltage the unit runs on before transferring to battery
 * = ds.vin_min
 *   ds.vin_min = 90 V  [DS-10449 Rev.09172021 p1 (120 V - 25%): "120 VAC, (-25% +15%)"] */
#define UPS_VIN_MIN_V              90.0f          /* 90 V */

/* Highest input voltage the unit accepts
 * = ds.vin_max
 *   ds.vin_max = 138 V  [DS-10449 Rev.09172021 p1 (120 V + 15%): "120 VAC, (-25% +15%)"] */
#define UPS_VIN_MAX_V              138.0f         /* 138 V */

/* Input current limit (data sheet maximum input current)
 * = ds.iin_max
 *   ds.iin_max = 7.9 A  [DS-10449 Rev.09172021 p1: "7.9 Amps"] */
#define UPS_IIN_LIMIT_A            7.9f           /* 7.9 A */

/* Lowest input frequency accepted (follower lock window / transfer to battery)
 * = ds.fin_nom_lo - ds.fin_tol_hz
 *   ds.fin_nom_lo = 60 Hz  [DS-10449 Rev.09172021 p1: "60 Hz, +/- 5.0 Hz"]
 *   ds.fin_tol_hz = 5 Hz  [DS-10449 Rev.09172021 p1: "60 Hz, +/- 5.0 Hz"] */
#define UPS_FIN_MIN_HZ             55.0f          /* 55 Hz */

/* Highest input frequency accepted (follower lock window / transfer to battery)
 * = ds.fin_nom_hi + ds.fin_tol_hz
 *   ds.fin_nom_hi = 60 Hz  [DS-10449 Rev.09172021 p1: "60 Hz, +/- 5.0 Hz"]
 *   ds.fin_tol_hz = 5 Hz  [DS-10449 Rev.09172021 p1: "60 Hz, +/- 5.0 Hz"] */
#define UPS_FIN_MAX_HZ             65.0f          /* 65 Hz */

/* ==== Rectifier / PFC ======================================================= */

/* A boost PFC stage must hold the bus above the peak of the highest input voltage
 * = sqrt(2) * vin_max */
#define UPS_VBUS_MIN_V             195.16147f     /* 195.161 V */

/* ==== DC bus ================================================================ */

/* DC bus regulation setpoint, bus minimum plus design margin, rounded up to 10 V
 * = ceil(vbus_min * (1 + design.vbus_margin) / 10) * 10
 *   design.vbus_margin = 7 %  [design fa10449.yaml] */
#define UPS_VBUS_SET_V             210.0f         /* 210 V */

/* Bus voltage at ADC full scale (divider ratio times ADC reference)
 * = target.v_ref * (board.vbus_r_top + board.vbus_r_bot) / board.vbus_r_bot
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.vbus_r_top = 1.5 Mohm  [board ups_ctrl_revA.yaml]
 *   board.vbus_r_bot = 10 kohm  [board ups_ctrl_revA.yaml] */
#define UPS_VBUS_FS_V              498.3f         /* 498.3 V */

/* Volts of bus per ADC count
 * = vbus_fs / target.adc_div
 *   target.adc_div = 4096 counts  [target f28004x.yaml] */
#define UPS_VBUS_V_PER_COUNT       0.12165527f    /* 0.121655 V/count */

/* ==== Inverter ============================================================== */

/* Output voltage setpoint (RMS); a selectable output option would be its own variant and header (none built here)
 * = ds.vout_nom
 *   ds.vout_nom = 120 V  [DS-10449 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_VOUT_SET_V             120.0f         /* 120 V */

/* Lower edge of the data sheet output regulation band
 * = vout_set * (1 - ds.vout_tol_pct)
 *   ds.vout_tol_pct = 3 %  [DS-10449 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_VOUT_LO_V              116.4f         /* 116.4 V */

/* Upper edge of the data sheet output regulation band
 * = vout_set * (1 + ds.vout_tol_pct)
 *   ds.vout_tol_pct = 3 %  [DS-10449 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_VOUT_HI_V              123.6f         /* 123.6 V */

/* Peak output voltage at the edge of the mid-rail-biased sense range
 * = target.v_ref / 2 * (board.vout_r_top + board.vout_r_bot) / board.vout_r_bot
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.vout_r_top = 1 Mohm  [board ups_ctrl_revA.yaml]
 *   board.vout_r_bot = 3.3 kohm  [board ups_ctrl_revA.yaml] */
#define UPS_VOUT_FS_PK_V           501.65f        /* 501.65 V */

/* Output frequency
 * = ds.fout_hz
 *   ds.fout_hz = 60 Hz  [DS-10449 Rev.09172021 p2: "60 Hz, Follower"] */
#define UPS_FOUT_HZ                60.0f          /* 60 Hz */

/* Changer regenerates a fixed frequency; follower tracks the input
 * = ds.fout_mode
 *   ds.fout_mode = follower  [DS-10449 Rev.09172021 p2: "60 Hz, Follower"] */
#define UPS_FOUT_MODE              UPS_FOUT_FOLLOWER

/* PWM period register, up-down (center-aligned) count mode as usual for inverters (TBPRD = f_clk / (2 f_sw))
 * = round(target.f_pwmclk / (2 * design.f_sw))
 *   target.f_pwmclk = 100 MHz  [target f28004x.yaml]
 *   design.f_sw = 20 kHz  [design fa10449.yaml] */
#define UPS_PWM_PERIOD_CNT         2500u          /* 2500 counts, uint16 */

/* Dead-time register
 * = ceil(design.t_deadband * target.f_pwmclk)
 *   design.t_deadband = 1 us  [design fa10449.yaml]
 *   target.f_pwmclk = 100 MHz  [target f28004x.yaml] */
#define UPS_PWM_DEADBAND_CNT       100u           /* 100 counts, uint16 */

/* ==== AC output ============================================================= */

/* Rated output current (RMS)
 * = ds.power_va / ds.vout_nom
 *   ds.power_va = 650 VA  [DS-10449 Rev.09172021 p1: "650 VA, 500 Watts"]
 *   ds.vout_nom = 120 V  [DS-10449 Rev.09172021 p1: "120 VAC, (+/-3%)"] */
#define UPS_IOUT_RATED_A           5.4166665f     /* 5.41667 A */

/* Overload alarm current (RMS)
 * = iout_rated * ds.overload_alarm_pct
 *   ds.overload_alarm_pct = 105 %  [DS-10449 Rev.09172021 p2: "Alarm at 105%, Shutdown at 115% of Full Load"] */
#define UPS_IOUT_ALARM_A           5.6875f        /* 5.6875 A */

/* Software overload trip level (RMS, timed; acts after UPS_OVERLOAD_DELAY_MS above this level)
 * = iout_rated * ds.overload_trip_pct
 *   ds.overload_trip_pct = 115 %  [DS-10449 Rev.09172021 p2: "Alarm at 105%, Shutdown at 115% of Full Load"] */
#define UPS_IOUT_TRIP_A            6.2291665f     /* 6.22917 A */

/* Time above the RMS trip level before the overload action (the data sheet gives no time)
 * = design.overload_delay
 *   design.overload_delay = 30 s  [design fa10449.yaml] */
#define UPS_OVERLOAD_DELAY_MS      30000u         /* 30000 ms, uint32 */

/* Hardware peak-current limit (fast comparator, short-circuit protection); must clear the crest factor of rated nonlinear loads
 * = design.pk_limit_factor * iout_rated
 *   design.pk_limit_factor = 3.5  [design fa10449.yaml] */
#define UPS_IOUT_PK_LIMIT_A        18.958332f     /* 18.9583 A */

/* Peak current at the edge of the mid-rail-biased current-sense range
 * = target.v_ref / 2 / (board.r_shunt * board.g_amp)
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.r_shunt = 2 mohm  [board ups_ctrl_revA.yaml]
 *   board.g_amp = 10  [board ups_ctrl_revA.yaml] */
#define UPS_IOUT_FS_PK_A           82.5f          /* 82.5 A */

/* Comparator DAC code for the positive hardware peak-current limit
 * = floor((target.v_ref / 2 + iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div)
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.r_shunt = 2 mohm  [board ups_ctrl_revA.yaml]
 *   board.g_amp = 10  [board ups_ctrl_revA.yaml]
 *   target.dac_div = 4096 counts  [target f28004x.yaml] */
#define UPS_IOUT_PKLIM_DAC_HI      2518u          /* 2518 counts, uint16 */

/* Comparator DAC code for the negative hardware peak-current limit
 * = ceil((target.v_ref / 2 - iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div)
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.r_shunt = 2 mohm  [board ups_ctrl_revA.yaml]
 *   board.g_amp = 10  [board ups_ctrl_revA.yaml]
 *   target.dac_div = 4096 counts  [target f28004x.yaml] */
#define UPS_IOUT_PKLIM_DAC_LO      1578u          /* 1578 counts, uint16 */

/* What the unit does when the RMS overload persists past the delay
 * = ds.overload_action
 *   ds.overload_action = shutdown  [DS-10449 Rev.09172021 p2: "Alarm at 105%, Shutdown at 115% of Full Load"] */
#define UPS_OVERLOAD_ACTION        UPS_OL_SHUTDOWN

/* ==== Battery =============================================================== */

/* Battery string nominal voltage
 * = ds.batt_string_v
 *   ds.batt_string_v = 92.4 V  [DS-10449 Rev.09172021 p2: "92.4 VDC"] */
#define UPS_VBAT_NOM_V             92.4f          /* 92.4 V */

/* Low-battery shutdown voltage
 * = ds.batt_series_cells * design.cell_cutoff_v
 *   ds.batt_series_cells = 28 cells  [DS-10449 Rev.09172021 p2: "28 S1P Batteries"]
 *   design.cell_cutoff_v = 2.5 V  [design fa10449.yaml] */
#define UPS_VBAT_CUTOFF_V          70.0f          /* 70 V */

/* Battery voltage at ADC full scale
 * = target.v_ref * (board.vbat_r_top + board.vbat_r_bot) / board.vbat_r_bot
 *   target.v_ref = 3.3 V  [target f28004x.yaml]
 *   board.vbat_r_top = 499 kohm  [board ups_ctrl_revA.yaml]
 *   board.vbat_r_bot = 10 kohm  [board ups_ctrl_revA.yaml] */
#define UPS_VBAT_FS_V              167.97f        /* 167.97 V */

/* ==== Control loop (engineer-supplied) ====================================== */

/* Voltage-loop proportional gain (tuned by power engineering)
 * = design.vloop_kp
 *   design.vloop_kp = 0.8  [design fa10449.yaml]
 *   engineer-supplied value, carried through unchanged */
/*   designed against: actual.f_sw = 20 kHz (staleness-tracked) */
#define UPS_VLOOP_KP               0.8f           /* 0.8 */

/* Voltage-loop integral gain per control ISR (tuned by power engineering)
 * = design.vloop_ki
 *   design.vloop_ki = 0.015  [design fa10449.yaml]
 *   engineer-supplied value, carried through unchanged */
/*   designed against: actual.f_sw = 20 kHz (staleness-tracked) */
#define UPS_VLOOP_KI               0.015f         /* 0.015 */

#endif /* CALGEN_FA10449_H */

Diff against committed version

No changes against the committed version.

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