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Results are representative and informational only. Under Texas Instruments' C2000 software license terms, real TI SDK source code is confidential and licensed for internal use only, so no TI code is included, displayed, processed, or emitted here. All C code on this site is synthetic, written for this demo, with invented names and values that resemble typical power-converter firmware. The generated headers compile against this demo's sample firmware in CI; the "legacy" files used for the audit are illustrative and not guaranteed to compile on any target. Product ratings come from public IntelliPower data sheets; all circuit values and gains are invented. Independent demo, not affiliated with or endorsed by AMETEK, IntelliPower, or Texas Instruments. TI, C2000, and Code Composer Studio are trademarks of Texas Instruments.
Review: fa10507_f2803x
FA10507 · IHT1500RM-M-1.25Kw-WRGlobal-FC60-120VAC-LiFeHS-3U16 · board ups_ctrl rev A · target F2803x (IQ20)
inputs sha256 a3d46fff83adcb604383d6d392f6048830b61b9182f9036436e22680d7f710f7
Constants 30/31Checks passData sheet 2 for reviewStaleness currentC generated · modeled checks passed
Constants
AC input
UPS_VIN_MIN_V89128960L
UPS_VIN_MAX_V277872640L
UPS_IIN_LIMIT_A20971520L
UPS_FIN_MIN_HZ49807360L
UPS_FIN_MAX_HZ66060288L
Rectifier / PFC
UPS_VBUS_MIN_V392971256L
DC bus
UPS_VBUS_SET_V429916160L
UPS_VBUS_FS_V522505421L
UPS_VBUS_V_PER_COUNT127565L
Inverter
UPS_VOUT_SET_V125829120L
UPS_VOUT_LO_V122054246L
UPS_VOUT_HI_V129603994L
UPS_VOUT_FS_PK_V526018150L
UPS_FOUT_HZ62914560L
UPS_FOUT_MODEUPS_FOUT_CHANGER
UPS_PWM_PERIOD_CNT1500u
UPS_PWM_DEADBAND_CNT60u
AC output
UPS_IOUT_RATED_A13107200L
UPS_IOUT_ALARM_An/a (not on data sheet)
UPS_IOUT_TRIP_A15728640L
UPS_OVERLOAD_DELAY_MS30000u
UPS_IOUT_PK_LIMIT_A45875200L
UPS_IOUT_FS_PK_A86507520L
UPS_IOUT_PKLIM_DAC_HI782u
UPS_IOUT_PKLIM_DAC_LO241u
UPS_OVERLOAD_ACTIONUPS_OL_SHUTDOWN
Battery
UPS_VBAT_NOM_V93952410L
UPS_VBAT_CUTOFF_V73400320L
UPS_VBAT_FS_V176129311L
Control loop (engineer-supplied)
UPS_VLOOP_KP838861L
UPS_VLOOP_KI15729L
Choose a constant to see how it's derived
UPS_VIN_MIN_V
Lowest input voltage the unit runs on before transferring to battery · pass
V_{\text{in,min}} = V_{\text{in,min}}^{\text{DS}} = 85\,\text{V}
Stored as iq20 → 89128960L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.vin_min | DS-10507 Rev.101119 p2 | 85 to 265VAC |
Generated C
/* Lowest input voltage the unit runs on before transferring to battery * = ds.vin_min * ds.vin_min = 85 V [DS-10507 Rev.101119 p2: "85 to 265VAC"] */ #define UPS_VIN_MIN_V 89128960L /* 85 V, iq20 */
UPS_VIN_MAX_V
Highest input voltage the unit accepts · pass
V_{\text{in,max}} = V_{\text{in,max}}^{\text{DS}} = 265\,\text{V}
Stored as iq20 → 277872640L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.vin_max | DS-10507 Rev.101119 p2 | 85 to 265VAC |
Generated C
/* Highest input voltage the unit accepts * = ds.vin_max * ds.vin_max = 265 V [DS-10507 Rev.101119 p2: "85 to 265VAC"] */ #define UPS_VIN_MAX_V 277872640L /* 265 V, iq20 */
UPS_IIN_LIMIT_A
Input current limit (data sheet maximum input current) · pass
I_{\text{in,max}} = I_{\text{in,max}}^{\text{DS}} = 20\,\text{A}
Stored as iq20 → 20971520L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.iin_max | DS-10507 Rev.101119 p2 | 20 Amps |
Generated C
/* Input current limit (data sheet maximum input current) * = ds.iin_max * ds.iin_max = 20 A [DS-10507 Rev.101119 p2: "20 Amps"] */ #define UPS_IIN_LIMIT_A 20971520L /* 20 A, iq20 */
UPS_FIN_MIN_HZ
Lowest input frequency accepted (follower lock window / transfer to battery) · pass
f_{\text{in,min}} = f_{\text{in,lo}} \cdot \left(1 - k_{f}\right)
= 50\,\text{Hz} \cdot \left(1 - 5\,\%\right)
= 47.5\,\text{Hz}
Stored as iq20 → 49807360L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.fin_nom_lo | DS-10507 Rev.101119 p2 | 50/60 Hz, (±5%) |
| ds.fin_tol_pct | DS-10507 Rev.101119 p2 | 50/60 Hz, (±5%) |
Generated C
/* Lowest input frequency accepted (follower lock window / transfer to battery) * = ds.fin_nom_lo * (1 - ds.fin_tol_pct) * ds.fin_nom_lo = 50 Hz [DS-10507 Rev.101119 p2: "50/60 Hz, (+/-5%)"] * ds.fin_tol_pct = 5 % [DS-10507 Rev.101119 p2: "50/60 Hz, (+/-5%)"] */ #define UPS_FIN_MIN_HZ 49807360L /* 47.5 Hz, iq20 */
UPS_FIN_MAX_HZ
Highest input frequency accepted (follower lock window / transfer to battery) · pass
f_{\text{in,max}} = f_{\text{in,hi}} \cdot \left(1 + k_{f}\right)
= 60\,\text{Hz} \cdot \left(1 + 5\,\%\right)
= 63\,\text{Hz}
Stored as iq20 → 66060288L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.fin_nom_hi | DS-10507 Rev.101119 p2 | 50/60 Hz, (±5%) |
| ds.fin_tol_pct | DS-10507 Rev.101119 p2 | 50/60 Hz, (±5%) |
Generated C
/* Highest input frequency accepted (follower lock window / transfer to battery) * = ds.fin_nom_hi * (1 + ds.fin_tol_pct) * ds.fin_nom_hi = 60 Hz [DS-10507 Rev.101119 p2: "50/60 Hz, (+/-5%)"] * ds.fin_tol_pct = 5 % [DS-10507 Rev.101119 p2: "50/60 Hz, (+/-5%)"] */ #define UPS_FIN_MAX_HZ 66060288L /* 63 Hz, iq20 */
UPS_VBUS_MIN_V
A boost PFC stage must hold the bus above the peak of the highest input voltage · pass
V_{\text{bus,min}} = \sqrt{2} \cdot V_{\text{in,max}}
= \sqrt{2} \cdot 265\,\text{V}
= 374.767\,\text{V}
Stored as iq20 → 392971256L, quantization error 2.56e-08% (round half to even).
Generated C
/* A boost PFC stage must hold the bus above the peak of the highest input voltage * = sqrt(2) * vin_max */ #define UPS_VBUS_MIN_V 392971256L /* 374.767 V, iq20, err 2.6e-08% */
UPS_VBUS_SET_V
DC bus regulation setpoint, bus minimum plus design margin, rounded up to 10 V · pass
V_{\text{bus,set}} = \left\lceil \frac{V_{\text{bus,min}} \cdot \left(1 + m_{\text{bus}}\right)}{10} \right\rceil \cdot 10
= \left\lceil \frac{374.767\,\text{V} \cdot \left(1 + 7\,\%\right)}{10} \right\rceil \cdot 10
= 410\,\text{V}
Stored as iq20 → 429916160L (exact).
| Input | From | Data sheet text |
|---|---|---|
| design.vbus_margin | design fa10507_f2803x.yaml | DC bus setpoint margin above rectified input peak |
Generated C
/* DC bus regulation setpoint, bus minimum plus design margin, rounded up to 10 V * = ceil(vbus_min * (1 + design.vbus_margin) / 10) * 10 * design.vbus_margin = 7 % [design fa10507_f2803x.yaml] */ #define UPS_VBUS_SET_V 429916160L /* 410 V, iq20 */
UPS_VBUS_FS_V
Bus voltage at ADC full scale (divider ratio times ADC reference) · pass
V_{\text{bus,FS}} = \frac{V_{\text{ref}} \cdot \left(R_{\text{bus,top}} + R_{\text{bus,bot}}\right)}{R_{\text{bus,bot}}}
= \frac{3.3\,\text{V} \cdot \left(1.5\,\mathrm{M}\Omega + 10\,\mathrm{k}\Omega\right)}{10\,\mathrm{k}\Omega}
= 498.3\,\text{V}
Stored as iq20 → 522505421L, quantization error 3.83e-08% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f2803x.yaml | fixed 0-3.3 V internal reference |
| board.vbus_r_top | board ups_ctrl_revA.yaml | DC bus divider |
| board.vbus_r_bot | board ups_ctrl_revA.yaml | DC bus divider |
Generated C
/* Bus voltage at ADC full scale (divider ratio times ADC reference) * = target.v_ref * (board.vbus_r_top + board.vbus_r_bot) / board.vbus_r_bot * target.v_ref = 3.3 V [target f2803x.yaml] * board.vbus_r_top = 1.5 Mohm [board ups_ctrl_revA.yaml] * board.vbus_r_bot = 10 kohm [board ups_ctrl_revA.yaml] */ #define UPS_VBUS_FS_V 522505421L /* 498.3 V, iq20, err 3.8e-08% */
UPS_VBUS_V_PER_COUNT
Volts of bus per ADC count · pass
k_{\text{bus}} = \frac{V_{\text{bus,FS}}}{D_{\text{ADC}}}
= \frac{498.3\,\text{V}}{4096}
= 0.121655\,\text{V/count}
Stored as iq20 → 127565L, quantization error 0.000157% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| target.adc_div | target f2803x.yaml | ADC transfer function: 1 LSB = V_ref / 4096 (TI SPRUGE5F 1.x) |
Generated C
/* Volts of bus per ADC count * = vbus_fs / target.adc_div * target.adc_div = 4096 counts [target f2803x.yaml] */ #define UPS_VBUS_V_PER_COUNT 127565L /* 0.121655 V/count, iq20, err 0.00016% */
UPS_VOUT_SET_V
Output voltage setpoint (RMS); a selectable output option would be its own variant and header (none built here) · pass
V_{\text{out}} = V_{\text{out,nom}} = 120\,\text{V}
Stored as iq20 → 125829120L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.vout_nom | DS-10507 Rev.101119 p2 | 120VAC, (±3%) Selectable (Optional 240VAC Output) |
Generated C
/* Output voltage setpoint (RMS); a selectable output option would be its own variant and header (none built here) * = ds.vout_nom * ds.vout_nom = 120 V [DS-10507 Rev.101119 p2: "120VAC, (+/-3%) Selectable (Optional 240VAC Output)"] */ #define UPS_VOUT_SET_V 125829120L /* 120 V, iq20 */
UPS_VOUT_LO_V
Lower edge of the data sheet output regulation band · pass
V_{\text{out,lo}} = V_{\text{out}} \cdot \left(1 - k_{\text{reg}}\right)
= 120\,\text{V} \cdot \left(1 - 3\,\%\right)
= 116.4\,\text{V}
Stored as iq20 → 122054246L, quantization error 3.28e-07% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| ds.vout_tol_pct | DS-10507 Rev.101119 p2 | 120VAC, (±3%) Selectable (Optional 240VAC Output) |
Generated C
/* Lower edge of the data sheet output regulation band * = vout_set * (1 - ds.vout_tol_pct) * ds.vout_tol_pct = 3 % [DS-10507 Rev.101119 p2: "120VAC, (+/-3%) Selectable (Optional 240VAC Output)"] */ #define UPS_VOUT_LO_V 122054246L /* 116.4 V, iq20, err 3.3e-07% */
UPS_VOUT_HI_V
Upper edge of the data sheet output regulation band · pass
V_{\text{out,hi}} = V_{\text{out}} \cdot \left(1 + k_{\text{reg}}\right)
= 120\,\text{V} \cdot \left(1 + 3\,\%\right)
= 123.6\,\text{V}
Stored as iq20 → 129603994L, quantization error 3.09e-07% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| ds.vout_tol_pct | DS-10507 Rev.101119 p2 | 120VAC, (±3%) Selectable (Optional 240VAC Output) |
Generated C
/* Upper edge of the data sheet output regulation band * = vout_set * (1 + ds.vout_tol_pct) * ds.vout_tol_pct = 3 % [DS-10507 Rev.101119 p2: "120VAC, (+/-3%) Selectable (Optional 240VAC Output)"] */ #define UPS_VOUT_HI_V 129603994L /* 123.6 V, iq20, err 3.1e-07% */
UPS_VOUT_FS_PK_V
Peak output voltage at the edge of the mid-rail-biased sense range · pass
V_{\text{out,FS}} = \frac{\frac{V_{\text{ref}}}{2} \cdot \left(R_{\text{out,top}} + R_{\text{out,bot}}\right)}{R_{\text{out,bot}}}
= \frac{\frac{3.3\,\text{V}}{2} \cdot \left(1\,\mathrm{M}\Omega + 3.3\,\mathrm{k}\Omega\right)}{3.3\,\mathrm{k}\Omega}
= 501.65\,\text{V}
Stored as iq20 → 526018150L, quantization error 7.6e-08% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f2803x.yaml | fixed 0-3.3 V internal reference |
| board.vout_r_top | board ups_ctrl_revA.yaml | AC output divider |
| board.vout_r_bot | board ups_ctrl_revA.yaml | AC output divider |
Generated C
/* Peak output voltage at the edge of the mid-rail-biased sense range * = target.v_ref / 2 * (board.vout_r_top + board.vout_r_bot) / board.vout_r_bot * target.v_ref = 3.3 V [target f2803x.yaml] * board.vout_r_top = 1 Mohm [board ups_ctrl_revA.yaml] * board.vout_r_bot = 3.3 kohm [board ups_ctrl_revA.yaml] */ #define UPS_VOUT_FS_PK_V 526018150L /* 501.65 V, iq20, err 7.6e-08% */
UPS_FOUT_HZ
Output frequency · pass
f_{\text{out}} = f_{\text{out}}^{\text{DS}} = 60\,\text{Hz}
Stored as iq20 → 62914560L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.fout_hz | DS-10507 Rev.101119 p2 | 60 Hz, Changer |
Generated C
/* Output frequency * = ds.fout_hz * ds.fout_hz = 60 Hz [DS-10507 Rev.101119 p2: "60 Hz, Changer"] */ #define UPS_FOUT_HZ 62914560L /* 60 Hz, iq20 */
UPS_FOUT_MODE
Changer regenerates a fixed frequency; follower tracks the input · pass
\texttt{UPS\_FOUT\_MODE} = \texttt{UPS\_FOUT\_CHANGER} \quad (\text{data sheet: changer})
| Input | From | Data sheet text |
|---|---|---|
| ds.fout_mode | DS-10507 Rev.101119 p2 | 60 Hz, Changer |
Generated C
/* Changer regenerates a fixed frequency; follower tracks the input * = ds.fout_mode * ds.fout_mode = changer [DS-10507 Rev.101119 p2: "60 Hz, Changer"] */ #define UPS_FOUT_MODE UPS_FOUT_CHANGER
UPS_PWM_PERIOD_CNT
PWM period register, up-down (center-aligned) count mode as usual for inverters (TBPRD = f_clk / (2 f_sw)) · pass
N_{\text{PWM}} = \operatorname{round}\!\left(\frac{f_{\text{clk}}}{2 \cdot f_{\text{sw}}}\right)
= \operatorname{round}\!\left(\frac{60\,\text{MHz}}{2 \cdot 20\,\text{kHz}}\right)
= \operatorname{round}\!\left(1500\right) = 1500
Stored as uint16 → 1500u (exact).
| Input | From | Data sheet text |
|---|---|---|
| target.f_pwmclk | target f2803x.yaml | ePWM clocked from SYSCLKOUT |
| design.f_sw | design fa10507_f2803x.yaml | inverter switching frequency (power engineering choice) |
Generated C
/* PWM period register, up-down (center-aligned) count mode as usual for inverters (TBPRD = f_clk / (2 f_sw)) * = round(target.f_pwmclk / (2 * design.f_sw)) * target.f_pwmclk = 60 MHz [target f2803x.yaml] * design.f_sw = 20 kHz [design fa10507_f2803x.yaml] */ #define UPS_PWM_PERIOD_CNT 1500u /* 1500 counts, uint16 */
UPS_PWM_DEADBAND_CNT
Dead-time register · pass
N_{\text{DB}} = \left\lceil t_{\text{DB}} \cdot f_{\text{clk}} \right\rceil
= \left\lceil 1\,\mu\mathrm{s} \cdot 60\,\text{MHz} \right\rceil
= \left\lceil 60 \right\rceil = 60
Stored as uint16 → 60u (exact).
| Input | From | Data sheet text |
|---|---|---|
| design.t_deadband | design fa10507_f2803x.yaml | gate-drive dead time for an IGBT bridge (power engineering choice) |
| target.f_pwmclk | target f2803x.yaml | ePWM clocked from SYSCLKOUT |
Generated C
/* Dead-time register * = ceil(design.t_deadband * target.f_pwmclk) * design.t_deadband = 1 us [design fa10507_f2803x.yaml] * target.f_pwmclk = 60 MHz [target f2803x.yaml] */ #define UPS_PWM_DEADBAND_CNT 60u /* 60 counts, uint16 */
UPS_IOUT_RATED_A
Rated output current (RMS) · pass
I_{\text{rated}} = \frac{S}{V_{\text{out,nom}}}
= \frac{1500\,\text{VA}}{120\,\text{V}}
= 12.5\,\text{A}
Stored as iq20 → 13107200L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.power_va | DS-10507 Rev.101119 p2 | 1500 VA, 1250 W |
| ds.vout_nom | DS-10507 Rev.101119 p2 | 120VAC, (±3%) Selectable (Optional 240VAC Output) |
Generated C
/* Rated output current (RMS) * = ds.power_va / ds.vout_nom * ds.power_va = 1500 VA [DS-10507 Rev.101119 p2: "1500 VA, 1250 W"] * ds.vout_nom = 120 V [DS-10507 Rev.101119 p2: "120VAC, (+/-3%) Selectable (Optional 240VAC Output)"] */ #define UPS_IOUT_RATED_A 13107200L /* 12.5 A, iq20 */
UPS_IOUT_ALARM_A
Overload alarm current (RMS) · n/a
input ds.overload_alarm_pct not in data sheet
I_{\text{alarm}} = I_{\text{rated}} \cdot k_{\text{alarm}}
Generated C
/* Overload alarm current (RMS) * = iout_rated * ds.overload_alarm_pct * NOT GENERATED: input ds.overload_alarm_pct not in data sheet */
UPS_IOUT_TRIP_A
Software overload trip level (RMS, timed; acts after UPS_OVERLOAD_DELAY_MS above this level) · pass
I_{\text{trip}} = I_{\text{rated}} \cdot k_{\text{trip}}
= 12.5\,\text{A} \cdot 120\,\%
= 15\,\text{A}
Stored as iq20 → 15728640L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.overload_trip_pct | DS-10507 Rev.101119 p2 (read as 120% of rated) | Shutdown at 20% Overload |
Generated C
/* Software overload trip level (RMS, timed; acts after UPS_OVERLOAD_DELAY_MS above this level) * = iout_rated * ds.overload_trip_pct * ds.overload_trip_pct = 120 % [DS-10507 Rev.101119 p2 (read as 120% of rated): "Shutdown at 20% Overload"] */ #define UPS_IOUT_TRIP_A 15728640L /* 15 A, iq20 */
UPS_OVERLOAD_DELAY_MS
Time above the RMS trip level before the overload action (the data sheet gives no time) · pass
t_{\text{OL}} = t_{\text{OL}}^{\text{design}} = 30000\,\text{ms}
Stored as uint32 → 30000u (exact).
| Input | From | Data sheet text |
|---|---|---|
| design.overload_delay | design fa10507_f2803x.yaml | time at the RMS trip level before the overload action; invented, the data sheet gives none |
Generated C
/* Time above the RMS trip level before the overload action (the data sheet gives no time) * = design.overload_delay * design.overload_delay = 30 s [design fa10507_f2803x.yaml] */ #define UPS_OVERLOAD_DELAY_MS 30000u /* 30000 ms, uint32 */
UPS_IOUT_PK_LIMIT_A
Hardware peak-current limit (fast comparator, short-circuit protection); must clear the crest factor of rated nonlinear loads · pass
I_{\text{pk,lim}} = k_{\text{pk}} \cdot I_{\text{rated}}
= 3.5 \cdot 12.5\,\text{A}
= 43.75\,\text{A}
Stored as iq20 → 45875200L (exact).
| Input | From | Data sheet text |
|---|---|---|
| design.pk_limit_factor | design fa10507_f2803x.yaml | hardware peak limit / rated RMS current: clears the rated crest factor with margin (checked) |
Generated C
/* Hardware peak-current limit (fast comparator, short-circuit protection); must clear the crest factor of rated nonlinear loads * = design.pk_limit_factor * iout_rated * design.pk_limit_factor = 3.5 [design fa10507_f2803x.yaml] */ #define UPS_IOUT_PK_LIMIT_A 45875200L /* 43.75 A, iq20 */
UPS_IOUT_FS_PK_A
Peak current at the edge of the mid-rail-biased current-sense range · pass
I_{\text{FS}} = \frac{\frac{V_{\text{ref}}}{2}}{R_{\text{sh}} \cdot G_{\text{amp}}}
= \frac{\frac{3.3\,\text{V}}{2}}{2\,\mathrm{m}\Omega \cdot 10}
= 82.5\,\text{A}
Stored as iq20 → 86507520L (exact).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f2803x.yaml | fixed 0-3.3 V internal reference |
| board.r_shunt | board ups_ctrl_revA.yaml | output current shunt; range must cover the hardware peak limit (~3.5x rated RMS) |
| board.g_amp | board ups_ctrl_revA.yaml | current-sense amplifier gain (rev A part) |
Generated C
/* Peak current at the edge of the mid-rail-biased current-sense range * = target.v_ref / 2 / (board.r_shunt * board.g_amp) * target.v_ref = 3.3 V [target f2803x.yaml] * board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml] * board.g_amp = 10 [board ups_ctrl_revA.yaml] */ #define UPS_IOUT_FS_PK_A 86507520L /* 82.5 A, iq20 */
UPS_IOUT_PKLIM_DAC_HI
Comparator DAC code for the positive hardware peak-current limit · pass
N_{\text{DAC,hi}} = \left\lfloor \frac{\frac{V_{\text{ref}}}{2} + I_{\text{pk,lim}} \cdot R_{\text{sh}} \cdot G_{\text{amp}}}{V_{\text{ref}}} \cdot D_{\text{DAC}} \right\rfloor
= \left\lfloor \frac{\frac{3.3\,\text{V}}{2} + 43.75\,\text{A} \cdot 2\,\mathrm{m}\Omega \cdot 10}{3.3\,\text{V}} \cdot 1023 \right\rfloor
= \left\lfloor 782.75 \right\rfloor = 782
Stored as uint16 → 782u (exact).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f2803x.yaml | fixed 0-3.3 V internal reference |
| board.r_shunt | board ups_ctrl_revA.yaml | output current shunt; range must cover the hardware peak limit (~3.5x rated RMS) |
| board.g_amp | board ups_ctrl_revA.yaml | current-sense amplifier gain (rev A part) |
| target.dac_div | target f2803x.yaml | comparator DAC: V = DACVAL x (VDDA - VSSA) / 1023 (TI SPRUGE5F 2.3.1; SPRUI10A DAC Reference) |
Generated C
/* Comparator DAC code for the positive hardware peak-current limit * = floor((target.v_ref / 2 + iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div) * target.v_ref = 3.3 V [target f2803x.yaml] * board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml] * board.g_amp = 10 [board ups_ctrl_revA.yaml] * target.dac_div = 1023 counts [target f2803x.yaml] */ #define UPS_IOUT_PKLIM_DAC_HI 782u /* 782 counts, uint16 */
UPS_IOUT_PKLIM_DAC_LO
Comparator DAC code for the negative hardware peak-current limit · pass
N_{\text{DAC,lo}} = \left\lceil \frac{\frac{V_{\text{ref}}}{2} - I_{\text{pk,lim}} \cdot R_{\text{sh}} \cdot G_{\text{amp}}}{V_{\text{ref}}} \cdot D_{\text{DAC}} \right\rceil
= \left\lceil \frac{\frac{3.3\,\text{V}}{2} - 43.75\,\text{A} \cdot 2\,\mathrm{m}\Omega \cdot 10}{3.3\,\text{V}} \cdot 1023 \right\rceil
= \left\lceil 240.25 \right\rceil = 241
Stored as uint16 → 241u (exact).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f2803x.yaml | fixed 0-3.3 V internal reference |
| board.r_shunt | board ups_ctrl_revA.yaml | output current shunt; range must cover the hardware peak limit (~3.5x rated RMS) |
| board.g_amp | board ups_ctrl_revA.yaml | current-sense amplifier gain (rev A part) |
| target.dac_div | target f2803x.yaml | comparator DAC: V = DACVAL x (VDDA - VSSA) / 1023 (TI SPRUGE5F 2.3.1; SPRUI10A DAC Reference) |
Generated C
/* Comparator DAC code for the negative hardware peak-current limit * = ceil((target.v_ref / 2 - iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div) * target.v_ref = 3.3 V [target f2803x.yaml] * board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml] * board.g_amp = 10 [board ups_ctrl_revA.yaml] * target.dac_div = 1023 counts [target f2803x.yaml] */ #define UPS_IOUT_PKLIM_DAC_LO 241u /* 241 counts, uint16 */
UPS_OVERLOAD_ACTION
What the unit does when the RMS overload persists past the delay · pass
\texttt{UPS\_OVERLOAD\_ACTION} = \texttt{UPS\_OL\_SHUTDOWN} \quad (\text{data sheet: shutdown})
| Input | From | Data sheet text |
|---|---|---|
| ds.overload_action | DS-10507 Rev.101119 p2 | Shutdown at 20% Overload |
Generated C
/* What the unit does when the RMS overload persists past the delay * = ds.overload_action * ds.overload_action = shutdown [DS-10507 Rev.101119 p2: "Shutdown at 20% Overload"] */ #define UPS_OVERLOAD_ACTION UPS_OL_SHUTDOWN
UPS_VBAT_NOM_V
Battery string nominal voltage · pass
V_{\text{bat}} = V_{\text{bat}}^{\text{DS}} = 89.6\,\text{V}
Stored as iq20 → 93952410L, quantization error 4.26e-07% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| ds.batt_string_v | DS-10507 Rev.101119 p2 | 89.6 VDC |
Generated C
/* Battery string nominal voltage * = ds.batt_string_v * ds.batt_string_v = 89.6 V [DS-10507 Rev.101119 p2: "89.6 VDC"] */ #define UPS_VBAT_NOM_V 93952410L /* 89.6 V, iq20, err 4.3e-07% */
UPS_VBAT_CUTOFF_V
Low-battery shutdown voltage · pass
V_{\text{bat,cut}} = n_{\text{cells}} \cdot V_{\text{cell,cut}}
= 28\,\text{cells} \cdot 2.5\,\text{V}
= 70\,\text{V}
Stored as iq20 → 73400320L (exact).
| Input | From | Data sheet text |
|---|---|---|
| ds.batt_series_cells | DS-10507 Rev.101119 p2 ("28SIP" read as 28S1P) | 28SIP |
| design.cell_cutoff_v | design fa10507_f2803x.yaml | LiFePO4 per-cell discharge cutoff, generic chemistry figure |
Generated C
/* Low-battery shutdown voltage
* = ds.batt_series_cells * design.cell_cutoff_v
* ds.batt_series_cells = 28 cells [DS-10507 Rev.101119 p2 ("28SIP" read as 28S1P): "28SIP"]
* design.cell_cutoff_v = 2.5 V [design fa10507_f2803x.yaml] */
#define UPS_VBAT_CUTOFF_V 73400320L /* 70 V, iq20 */UPS_VBAT_FS_V
Battery voltage at ADC full scale · pass
V_{\text{bat,FS}} = \frac{V_{\text{ref}} \cdot \left(R_{\text{bat,top}} + R_{\text{bat,bot}}\right)}{R_{\text{bat,bot}}}
= \frac{3.3\,\text{V} \cdot \left(499\,\mathrm{k}\Omega + 10\,\mathrm{k}\Omega\right)}{10\,\mathrm{k}\Omega}
= 167.97\,\text{V}
Stored as iq20 → 176129311L, quantization error 1.59e-07% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| target.v_ref | target f2803x.yaml | fixed 0-3.3 V internal reference |
| board.vbat_r_top | board ups_ctrl_revA.yaml | battery divider |
| board.vbat_r_bot | board ups_ctrl_revA.yaml | battery divider |
Generated C
/* Battery voltage at ADC full scale * = target.v_ref * (board.vbat_r_top + board.vbat_r_bot) / board.vbat_r_bot * target.v_ref = 3.3 V [target f2803x.yaml] * board.vbat_r_top = 499 kohm [board ups_ctrl_revA.yaml] * board.vbat_r_bot = 10 kohm [board ups_ctrl_revA.yaml] */ #define UPS_VBAT_FS_V 176129311L /* 167.97 V, iq20, err 1.6e-07% */
UPS_VLOOP_KP
Voltage-loop proportional gain (tuned by power engineering) · pass
K_P = 0.8 \quad (\text{engineer-supplied})
Stored as iq20 → 838861L, quantization error 2.38e-05% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| design.vloop_kp | design fa10507_f2803x.yaml | voltage-loop proportional gain (engineer-tuned, invented) |
Generated C
/* Voltage-loop proportional gain (tuned by power engineering) * = design.vloop_kp * design.vloop_kp = 0.8 [design fa10507_f2803x.yaml] * engineer-supplied value, carried through unchanged */ #define UPS_VLOOP_KP 838861L /* 0.8, iq20, err 2.4e-05% */
UPS_VLOOP_KI
Voltage-loop integral gain per control ISR (tuned by power engineering) · pass
K_I = 0.015 \quad (\text{engineer-supplied})
Stored as iq20 → 15729L, quantization error 0.00229% (round half to even).
| Input | From | Data sheet text |
|---|---|---|
| design.vloop_ki | design fa10507_f2803x.yaml | voltage-loop integral gain per ISR (engineer-tuned, invented) |
Generated C
/* Voltage-loop integral gain per control ISR (tuned by power engineering) * = design.vloop_ki * design.vloop_ki = 0.015 [design fa10507_f2803x.yaml] * engineer-supplied value, carried through unchanged */ #define UPS_VLOOP_KI 15729L /* 0.0150003, iq20, err 0.0023% */
Checks
| Check | Math | |
|---|---|---|
| pass | bus_above_output_peak The output peak at the top of the regulation band must fit under the bus at the inverter's maximum modulation index (room for modulation limits, dead time and device drop) | \sqrt{2} \cdot V_{\text{out,hi}} \le m_{\max} \cdot V_{\text{bus,set}} \cdot k_{\text{bridge}} = \sqrt{2} \cdot 123.6\,\text{V} \le 95\,\% \cdot 410\,\text{V} \cdot 0.5 \Rightarrow 174.797\,\text{V} \le 194.75\,\text{V}\quad \checkmark |
| pass | bus_sense_range Bus setpoint must sit inside the bus sensor's range with headroom | V_{\text{bus,set}} \le h \cdot V_{\text{bus,FS}} = 410\,\text{V} \le 95\,\% \cdot 498.3\,\text{V} \Rightarrow 410\,\text{V} \le 473.385\,\text{V}\quad \checkmark |
| pass | vout_sense_range Output peak at the top of the regulation band must sit inside the output sensor's range | \sqrt{2} \cdot V_{\text{out,hi}} \le h \cdot V_{\text{out,FS}} = \sqrt{2} \cdot 123.6\,\text{V} \le 95\,\% \cdot 501.65\,\text{V} \Rightarrow 174.797\,\text{V} \le 476.567\,\text{V}\quad \checkmark |
| pass | iout_sense_range Hardware peak limit must sit inside the current sensor's range, or the sensor saturates before the limit fires | I_{\text{pk,lim}} \le h \cdot I_{\text{FS}} = 43.75\,\text{A} \le 95\,\% \cdot 82.5\,\text{A} \Rightarrow 43.75\,\text{A} \le 78.375\,\text{A}\quad \checkmark |
| pass | overload_below_pk_limit A sinusoidal overload at the RMS trip level must stay under the hardware limit, so the timed overload acts first (crest-factor loads above rated are clipped by the hardware limit, as on real units) | \sqrt{2} \cdot I_{\text{trip}} < I_{\text{pk,lim}} = \sqrt{2} \cdot 15\,\text{A} < 43.75\,\text{A} \Rightarrow 21.2132\,\text{A} < 43.75\,\text{A}\quad \checkmark |
| pass | crest_clears_pk_limit The peak of a rated nonlinear load (the assumed 3:1 crest factor at rated current) must clear the hardware limit, or normal loads trip the fast protection | CF \cdot I_{\text{rated}} < I_{\text{pk,lim}} = 3 \cdot 12.5\,\text{A} < 43.75\,\text{A} \Rightarrow 37.5\,\text{A} < 43.75\,\text{A}\quad \checkmark |
| pass | crest_clears_dac_hi The DAC-derived positive trip threshold must clear the rated illustrative load peak after quantization | CF \cdot I_{\text{rated}} < \frac{\left(\frac{N_{\text{DAC,hi}}}{D_{\text{DAC}}} - 0.5\right) \cdot V_{\text{ref}}}{R_{\text{sh}} \cdot G_{\text{amp}}} = 3 \cdot 12.5\,\text{A} < \frac{\left(\frac{782}{1023} - 0.5\right) \cdot 3.3\,\text{V}}{2\,\mathrm{m}\Omega \cdot 10} \Rightarrow 37.5\,\text{A} < 43.629\,\text{A}\quad \checkmark |
| pass | crest_clears_dac_lo The magnitude of the DAC-derived negative trip threshold must clear the rated illustrative load peak after quantization | CF \cdot I_{\text{rated}} < \frac{\left(0.5 - \frac{N_{\text{DAC,lo}}}{D_{\text{DAC}}}\right) \cdot V_{\text{ref}}}{R_{\text{sh}} \cdot G_{\text{amp}}} = 3 \cdot 12.5\,\text{A} < \frac{\left(0.5 - \frac{241}{1023}\right) \cdot 3.3\,\text{V}}{2\,\mathrm{m}\Omega \cdot 10} \Rightarrow 37.5\,\text{A} < 43.629\,\text{A}\quad \checkmark |
| pass | dac_hi_in_range Positive peak-limit DAC code must exist on this chip's comparator DAC | N_{\text{DAC,hi}} \le N_{\text{DAC}} \Rightarrow 782 \le 1023\quad \checkmark |
| pass | deadband_in_range Dead-time count must fit this chip's dead-band counter | N_{\text{DB}} \le N_{\text{DB,max}} \Rightarrow 60 \le 1023\quad \checkmark |
| n/a | alarm_below_trip Overload alarm must come before the trip | I_{\text{alarm}} < I_{\text{trip}} \quad (\text{not applicable}) |
| pass | vbat_sense_range A fully charged battery must sit inside the battery sensor's range | n_{\text{cells}} \cdot V_{\text{cell,full}} \le h \cdot V_{\text{bat,FS}} = 28\,\text{cells} \cdot 3.65\,\text{V} \le 95\,\% \cdot 167.97\,\text{V} \Rightarrow 102.2\,\text{V} \le 159.572\,\text{V}\quad \checkmark |
| pass | cutoff_below_nominal Low-battery cutoff must be below nominal | V_{\text{bat,cut}} < V_{\text{bat}} \Rightarrow 70\,\text{V} < 89.6\,\text{V}\quad \checkmark |
| pass | input_voltage_order Minimum input voltage must not exceed maximum input voltage | V_{\text{in,min}}^{\text{DS}} \le V_{\text{in,max}}^{\text{DS}} \Rightarrow 85\,\text{V} \le 265\,\text{V}\quad \checkmark |
| pass | input_frequency_order Lower nominal input frequency must not exceed the upper frequency | f_{\text{in,lo}} \le f_{\text{in,hi}} \Rightarrow 50\,\text{Hz} \le 60\,\text{Hz}\quad \checkmark |
| pass | battery_cells_integer Battery series cell count must be a whole number | n_{\text{cells}} = \operatorname{round}\!\left(n_{\text{cells}}\right) = 28\,\text{cells} = \operatorname{round}\!\left(28\,\text{cells}\right) \Rightarrow 28 = 28\quad \checkmark |
| pass | battery_cells_positive Battery series cell count must be positive | n_{\text{cells}} > 0 = 28\,\text{cells} > 0 \Rightarrow 28 > 0\quad \checkmark |
| pass | output_regulation_nonnegative Output regulation tolerance must not be negative | k_{\text{reg}} \ge 0 = 3\,\% \ge 0 \Rightarrow 0.03 \ge 0\quad \checkmark |
| pass | output_regulation_below_100 Output regulation tolerance must be below 100% | k_{\text{reg}} < 1 = 3\,\% < 1 \Rightarrow 0.03 < 1\quad \checkmark |
Data sheet consistency
| Finding | Handling | |
|---|---|---|
| flagged | isolation row says Isolated but this model string has no 'Isolated' token “IHT1500RM-M-1.25Kw-WRGlobal-FC60-120VAC-LiFeHS-3U16” “Isolated” | needs engineer review |
| flagged | the two printed model numbers differ (page-1 only: Isolated, 120; table only: 120VAC) “IHT1500RM-M-1.25Kw-WRGlobal-Isolated-FC60-120-LiFeHS-3U16” “IHT1500RM-M-1.25Kw-WRGlobal-FC60-120VAC-LiFeHS-3U16” | needs engineer review |
Staleness of engineer-supplied values
| Value | Design basis | |
|---|---|---|
| pass | design.vloop_kp | designed for actual.f_sw = 20 kHz; now 20 kHz |
| pass | design.vloop_ki | designed for actual.f_sw = 20 kHz; now 20 kHz |
Generated C
calgen_fa10507_f2803x.h (216 lines)
/* GENERATED by calgen 0.1.0 -- DO NOT EDIT. Regenerate from the spec files.
*
* variant : fa10507_f2803x
* product : FA10507 IHT1500RM-M-1.25Kw-WRGlobal-FC60-120VAC-LiFeHS-3U16
* ratings from DS-10507 Rev.101119 (public IntelliPower data sheet)
* board : ups_ctrl rev A
* target : f2803x (default format iq20)
* inverter: Half bridge - bipolar PWM (assumed hardware profile)
* PWM Hz : requested 20000; achieved 20000
* inputs : sha256 a3d46fff83adcb604383d6d392f6048830b61b9182f9036436e22680d7f710f7
*
* SYNTHETIC DEMO: firmware names and circuit values are invented; product ratings
* come from the public data sheet cited above. Not from any vendor SDK.
*/
#ifndef CALGEN_FA10507_F2803X_H
#define CALGEN_FA10507_F2803X_H
#include "calgen_types.h"
#define CALGEN_GLOBAL_Q 20 /* fixed-point target: values below are IQ20 integers */
typedef calgen_iq_t calgen_num_t; /* measurements are compared as IQ20 integers, no float */
#define CALGEN_NUM(x) ((calgen_num_t)((x) * 1048576.0 + ((x) >= 0 ? 0.5 : -0.5))) /* rounds to nearest (ties away from zero; the generator ties to even); float constant expressions only */
#define CALGEN_REAL(x) ((float)(x) / 1048576.0f) /* host-side checks only */
/* ==== AC input ============================================================== */
/* Lowest input voltage the unit runs on before transferring to battery
* = ds.vin_min
* ds.vin_min = 85 V [DS-10507 Rev.101119 p2: "85 to 265VAC"] */
#define UPS_VIN_MIN_V 89128960L /* 85 V, iq20 */
/* Highest input voltage the unit accepts
* = ds.vin_max
* ds.vin_max = 265 V [DS-10507 Rev.101119 p2: "85 to 265VAC"] */
#define UPS_VIN_MAX_V 277872640L /* 265 V, iq20 */
/* Input current limit (data sheet maximum input current)
* = ds.iin_max
* ds.iin_max = 20 A [DS-10507 Rev.101119 p2: "20 Amps"] */
#define UPS_IIN_LIMIT_A 20971520L /* 20 A, iq20 */
/* Lowest input frequency accepted (follower lock window / transfer to battery)
* = ds.fin_nom_lo * (1 - ds.fin_tol_pct)
* ds.fin_nom_lo = 50 Hz [DS-10507 Rev.101119 p2: "50/60 Hz, (+/-5%)"]
* ds.fin_tol_pct = 5 % [DS-10507 Rev.101119 p2: "50/60 Hz, (+/-5%)"] */
#define UPS_FIN_MIN_HZ 49807360L /* 47.5 Hz, iq20 */
/* Highest input frequency accepted (follower lock window / transfer to battery)
* = ds.fin_nom_hi * (1 + ds.fin_tol_pct)
* ds.fin_nom_hi = 60 Hz [DS-10507 Rev.101119 p2: "50/60 Hz, (+/-5%)"]
* ds.fin_tol_pct = 5 % [DS-10507 Rev.101119 p2: "50/60 Hz, (+/-5%)"] */
#define UPS_FIN_MAX_HZ 66060288L /* 63 Hz, iq20 */
/* ==== Rectifier / PFC ======================================================= */
/* A boost PFC stage must hold the bus above the peak of the highest input voltage
* = sqrt(2) * vin_max */
#define UPS_VBUS_MIN_V 392971256L /* 374.767 V, iq20, err 2.6e-08% */
/* ==== DC bus ================================================================ */
/* DC bus regulation setpoint, bus minimum plus design margin, rounded up to 10 V
* = ceil(vbus_min * (1 + design.vbus_margin) / 10) * 10
* design.vbus_margin = 7 % [design fa10507_f2803x.yaml] */
#define UPS_VBUS_SET_V 429916160L /* 410 V, iq20 */
/* Bus voltage at ADC full scale (divider ratio times ADC reference)
* = target.v_ref * (board.vbus_r_top + board.vbus_r_bot) / board.vbus_r_bot
* target.v_ref = 3.3 V [target f2803x.yaml]
* board.vbus_r_top = 1.5 Mohm [board ups_ctrl_revA.yaml]
* board.vbus_r_bot = 10 kohm [board ups_ctrl_revA.yaml] */
#define UPS_VBUS_FS_V 522505421L /* 498.3 V, iq20, err 3.8e-08% */
/* Volts of bus per ADC count
* = vbus_fs / target.adc_div
* target.adc_div = 4096 counts [target f2803x.yaml] */
#define UPS_VBUS_V_PER_COUNT 127565L /* 0.121655 V/count, iq20, err 0.00016% */
/* ==== Inverter ============================================================== */
/* Output voltage setpoint (RMS); a selectable output option would be its own variant and header (none built here)
* = ds.vout_nom
* ds.vout_nom = 120 V [DS-10507 Rev.101119 p2: "120VAC, (+/-3%) Selectable (Optional 240VAC Output)"] */
#define UPS_VOUT_SET_V 125829120L /* 120 V, iq20 */
/* Lower edge of the data sheet output regulation band
* = vout_set * (1 - ds.vout_tol_pct)
* ds.vout_tol_pct = 3 % [DS-10507 Rev.101119 p2: "120VAC, (+/-3%) Selectable (Optional 240VAC Output)"] */
#define UPS_VOUT_LO_V 122054246L /* 116.4 V, iq20, err 3.3e-07% */
/* Upper edge of the data sheet output regulation band
* = vout_set * (1 + ds.vout_tol_pct)
* ds.vout_tol_pct = 3 % [DS-10507 Rev.101119 p2: "120VAC, (+/-3%) Selectable (Optional 240VAC Output)"] */
#define UPS_VOUT_HI_V 129603994L /* 123.6 V, iq20, err 3.1e-07% */
/* Peak output voltage at the edge of the mid-rail-biased sense range
* = target.v_ref / 2 * (board.vout_r_top + board.vout_r_bot) / board.vout_r_bot
* target.v_ref = 3.3 V [target f2803x.yaml]
* board.vout_r_top = 1 Mohm [board ups_ctrl_revA.yaml]
* board.vout_r_bot = 3.3 kohm [board ups_ctrl_revA.yaml] */
#define UPS_VOUT_FS_PK_V 526018150L /* 501.65 V, iq20, err 7.6e-08% */
/* Output frequency
* = ds.fout_hz
* ds.fout_hz = 60 Hz [DS-10507 Rev.101119 p2: "60 Hz, Changer"] */
#define UPS_FOUT_HZ 62914560L /* 60 Hz, iq20 */
/* Changer regenerates a fixed frequency; follower tracks the input
* = ds.fout_mode
* ds.fout_mode = changer [DS-10507 Rev.101119 p2: "60 Hz, Changer"] */
#define UPS_FOUT_MODE UPS_FOUT_CHANGER
/* PWM period register, up-down (center-aligned) count mode as usual for inverters (TBPRD = f_clk / (2 f_sw))
* = round(target.f_pwmclk / (2 * design.f_sw))
* target.f_pwmclk = 60 MHz [target f2803x.yaml]
* design.f_sw = 20 kHz [design fa10507_f2803x.yaml] */
#define UPS_PWM_PERIOD_CNT 1500u /* 1500 counts, uint16 */
/* Dead-time register
* = ceil(design.t_deadband * target.f_pwmclk)
* design.t_deadband = 1 us [design fa10507_f2803x.yaml]
* target.f_pwmclk = 60 MHz [target f2803x.yaml] */
#define UPS_PWM_DEADBAND_CNT 60u /* 60 counts, uint16 */
/* ==== AC output ============================================================= */
/* Rated output current (RMS)
* = ds.power_va / ds.vout_nom
* ds.power_va = 1500 VA [DS-10507 Rev.101119 p2: "1500 VA, 1250 W"]
* ds.vout_nom = 120 V [DS-10507 Rev.101119 p2: "120VAC, (+/-3%) Selectable (Optional 240VAC Output)"] */
#define UPS_IOUT_RATED_A 13107200L /* 12.5 A, iq20 */
/* Overload alarm current (RMS)
* = iout_rated * ds.overload_alarm_pct
* NOT GENERATED: input ds.overload_alarm_pct not in data sheet */
/* Software overload trip level (RMS, timed; acts after UPS_OVERLOAD_DELAY_MS above this level)
* = iout_rated * ds.overload_trip_pct
* ds.overload_trip_pct = 120 % [DS-10507 Rev.101119 p2 (read as 120% of rated): "Shutdown at 20% Overload"] */
#define UPS_IOUT_TRIP_A 15728640L /* 15 A, iq20 */
/* Time above the RMS trip level before the overload action (the data sheet gives no time)
* = design.overload_delay
* design.overload_delay = 30 s [design fa10507_f2803x.yaml] */
#define UPS_OVERLOAD_DELAY_MS 30000u /* 30000 ms, uint32 */
/* Hardware peak-current limit (fast comparator, short-circuit protection); must clear the crest factor of rated nonlinear loads
* = design.pk_limit_factor * iout_rated
* design.pk_limit_factor = 3.5 [design fa10507_f2803x.yaml] */
#define UPS_IOUT_PK_LIMIT_A 45875200L /* 43.75 A, iq20 */
/* Peak current at the edge of the mid-rail-biased current-sense range
* = target.v_ref / 2 / (board.r_shunt * board.g_amp)
* target.v_ref = 3.3 V [target f2803x.yaml]
* board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml]
* board.g_amp = 10 [board ups_ctrl_revA.yaml] */
#define UPS_IOUT_FS_PK_A 86507520L /* 82.5 A, iq20 */
/* Comparator DAC code for the positive hardware peak-current limit
* = floor((target.v_ref / 2 + iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div)
* target.v_ref = 3.3 V [target f2803x.yaml]
* board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml]
* board.g_amp = 10 [board ups_ctrl_revA.yaml]
* target.dac_div = 1023 counts [target f2803x.yaml] */
#define UPS_IOUT_PKLIM_DAC_HI 782u /* 782 counts, uint16 */
/* Comparator DAC code for the negative hardware peak-current limit
* = ceil((target.v_ref / 2 - iout_pk_limit * board.r_shunt * board.g_amp) / target.v_ref * target.dac_div)
* target.v_ref = 3.3 V [target f2803x.yaml]
* board.r_shunt = 2 mohm [board ups_ctrl_revA.yaml]
* board.g_amp = 10 [board ups_ctrl_revA.yaml]
* target.dac_div = 1023 counts [target f2803x.yaml] */
#define UPS_IOUT_PKLIM_DAC_LO 241u /* 241 counts, uint16 */
/* What the unit does when the RMS overload persists past the delay
* = ds.overload_action
* ds.overload_action = shutdown [DS-10507 Rev.101119 p2: "Shutdown at 20% Overload"] */
#define UPS_OVERLOAD_ACTION UPS_OL_SHUTDOWN
/* ==== Battery =============================================================== */
/* Battery string nominal voltage
* = ds.batt_string_v
* ds.batt_string_v = 89.6 V [DS-10507 Rev.101119 p2: "89.6 VDC"] */
#define UPS_VBAT_NOM_V 93952410L /* 89.6 V, iq20, err 4.3e-07% */
/* Low-battery shutdown voltage
* = ds.batt_series_cells * design.cell_cutoff_v
* ds.batt_series_cells = 28 cells [DS-10507 Rev.101119 p2 ("28SIP" read as 28S1P): "28SIP"]
* design.cell_cutoff_v = 2.5 V [design fa10507_f2803x.yaml] */
#define UPS_VBAT_CUTOFF_V 73400320L /* 70 V, iq20 */
/* Battery voltage at ADC full scale
* = target.v_ref * (board.vbat_r_top + board.vbat_r_bot) / board.vbat_r_bot
* target.v_ref = 3.3 V [target f2803x.yaml]
* board.vbat_r_top = 499 kohm [board ups_ctrl_revA.yaml]
* board.vbat_r_bot = 10 kohm [board ups_ctrl_revA.yaml] */
#define UPS_VBAT_FS_V 176129311L /* 167.97 V, iq20, err 1.6e-07% */
/* ==== Control loop (engineer-supplied) ====================================== */
/* Voltage-loop proportional gain (tuned by power engineering)
* = design.vloop_kp
* design.vloop_kp = 0.8 [design fa10507_f2803x.yaml]
* engineer-supplied value, carried through unchanged */
/* designed against: actual.f_sw = 20 kHz (staleness-tracked) */
#define UPS_VLOOP_KP 838861L /* 0.8, iq20, err 2.4e-05% */
/* Voltage-loop integral gain per control ISR (tuned by power engineering)
* = design.vloop_ki
* design.vloop_ki = 0.015 [design fa10507_f2803x.yaml]
* engineer-supplied value, carried through unchanged */
/* designed against: actual.f_sw = 20 kHz (staleness-tracked) */
#define UPS_VLOOP_KI 15729L /* 0.0150003, iq20, err 0.0023% */
#endif /* CALGEN_FA10507_F2803X_H */
Diff against committed version
No changes against the committed version.
Reviewed by
Date
Decision: approve / reject / waiver